DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & 0) == 0.

Fixes PR16083.

llvm-svn: 182357

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -1162,7 +1162,8 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
       }
 
       // Make sure we're not losing bits from the constant.
-      if (MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) {
+      if (MinBits > 0 &&
+          MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) {
         EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
         if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
           // Will get folded away.

llvm/test/CodeGen/X86/shrink-compare.ll

@@ -50,3 +50,19 @@ if.end:
 ; CHECK: test3:
 ; CHECK: cmpb $-1, %{{dil|cl}}
 }
+
+; PR16083
+define i1 @test4(i64 %a, i32 %b) {
+entry:
+  %tobool = icmp ne i32 %b, 0
+  br i1 %tobool, label %lor.end, label %lor.rhs
+
+lor.rhs:                                          ; preds = %entry
+  %and = and i64 0, %a
+  %tobool1 = icmp ne i64 %and, 0
+  br label %lor.end
+
+lor.end:                                          ; preds = %lor.rhs, %entry
+  %p = phi i1 [ true, %entry ], [ %tobool1, %lor.rhs ]
+  ret i1 %p
+}