[Hexagon] Early-if-convert branches that may exit the loop
Merge the tail block into the loop in cases where the main loop body
exits early, subject to profitability constraints. This will coalesce
the loop body into fewer blocks.
For example:
loop: loop:
// loop body // loop body
if (...) jump exit --> // more body
more: if (...) jump exit
// more body jump loop
jump loop
llvm-svn: 297033
This commit is contained in:
Krzysztof Parzyszek
parent
e16ce15687
commit
8a4c601abc
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@ -105,6 +105,8 @@ namespace {
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cl::init(false), cl::desc("Enable branch probability info"));
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cl::opt<unsigned> SizeLimit("eif-limit", cl::init(6), cl::Hidden,
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cl::desc("Size limit in Hexagon early if-conversion"));
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cl::opt<bool> SkipExitBranches("eif-no-loop-exit", cl::init(false),
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cl::Hidden, cl::desc("Do not convert branches that may exit the loop"));
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struct PrintMB {
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PrintMB(const MachineBasicBlock *B) : MB(B) {}
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@ -142,8 +144,8 @@ namespace {
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raw_ostream &operator<<(raw_ostream &OS, const PrintFP &P) {
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OS << "{ SplitB:" << PrintMB(P.FP.SplitB)
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<< ", PredR:" << PrintReg(P.FP.PredR, &P.TRI)
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<< ", TrueB:" << PrintMB(P.FP.TrueB) << ", FalseB:"
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<< PrintMB(P.FP.FalseB)
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<< ", TrueB:" << PrintMB(P.FP.TrueB)
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<< ", FalseB:" << PrintMB(P.FP.FalseB)
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<< ", JoinB:" << PrintMB(P.FP.JoinB) << " }";
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return OS;
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}
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@ -187,7 +189,8 @@ namespace {
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bool usesUndefVReg(const MachineInstr *MI) const;
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bool isValid(const FlowPattern &FP) const;
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unsigned countPredicateDefs(const MachineBasicBlock *B) const;
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unsigned computePhiCost(MachineBasicBlock *B) const;
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unsigned computePhiCost(const MachineBasicBlock *B,
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const FlowPattern &FP) const;
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bool isProfitable(const FlowPattern &FP) const;
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bool isPredicableStore(const MachineInstr *MI) const;
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bool isSafeToSpeculate(const MachineInstr *MI) const;
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@ -199,6 +202,9 @@ namespace {
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MachineBasicBlock::iterator At, MachineBasicBlock *FromB,
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unsigned PredR, bool IfTrue);
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unsigned buildMux(MachineBasicBlock *B, MachineBasicBlock::iterator At,
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const TargetRegisterClass *DRC, unsigned PredR, unsigned TR,
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unsigned TSR, unsigned FR, unsigned FSR);
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void updatePhiNodes(MachineBasicBlock *WhereB, const FlowPattern &FP);
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void convert(const FlowPattern &FP);
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@ -230,7 +236,7 @@ bool HexagonEarlyIfConversion::isPreheader(const MachineBasicBlock *B) const {
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return false;
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MachineBasicBlock *SB = *B->succ_begin();
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MachineLoop *L = MLI->getLoopFor(SB);
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return L && SB == L->getHeader();
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return L && SB == L->getHeader() && MDT->dominates(B, SB);
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}
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bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B,
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@ -264,9 +270,6 @@ bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B,
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// mark as diamond with both sides equal?
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return false;
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}
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// Loop could be null for both.
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if (MLI->getLoopFor(T1B) != L || MLI->getLoopFor(T2B) != L)
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return false;
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// Record the true/false blocks in such a way that "true" means "if (PredR)",
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// and "false" means "if (!PredR)".
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@ -289,8 +292,14 @@ bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B,
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// it has a single successor. In fact, the block has to end either with
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// an unconditional branch (which can be predicated), or with a fall-
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// through.
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bool TOk = (TNP == 1) && (TNS == 1);
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bool FOk = (FNP == 1) && (FNS == 1);
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// Also, skip blocks that do not belong to the same loop.
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bool TOk = (TNP == 1 && TNS == 1 && MLI->getLoopFor(TB) == L);
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bool FOk = (FNP == 1 && FNS == 1 && MLI->getLoopFor(FB) == L);
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// If requested (via an option), do not consider branches where the
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// true and false targets do not belong to the same loop.
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if (SkipExitBranches && MLI->getLoopFor(TB) != MLI->getLoopFor(FB))
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return false;
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// If neither is predicable, there is nothing interesting.
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if (!TOk && !FOk)
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@ -307,18 +316,16 @@ bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B,
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// Diamond: "if (P) then TB; else FB;".
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} else {
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// TOk && !FOk
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if (TSB == FB) {
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if (TSB == FB)
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JB = FB;
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FB = nullptr;
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}
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}
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} else {
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// !TOk && FOk (at least one must be true by now).
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if (FSB == TB) {
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if (FSB == TB)
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JB = TB;
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TB = nullptr;
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}
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}
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// Don't try to predicate loop preheaders.
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if ((TB && isPreheader(TB)) || (FB && isPreheader(FB))) {
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DEBUG(dbgs() << "One of blocks " << PrintMB(TB) << ", " << PrintMB(FB)
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@ -448,24 +455,39 @@ bool HexagonEarlyIfConversion::isValid(const FlowPattern &FP) const {
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return true;
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}
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unsigned HexagonEarlyIfConversion::computePhiCost(MachineBasicBlock *B) const {
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assert(B->pred_size() <= 2);
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unsigned HexagonEarlyIfConversion::computePhiCost(const MachineBasicBlock *B,
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const FlowPattern &FP) const {
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if (B->pred_size() < 2)
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return 0;
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unsigned Cost = 0;
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MachineBasicBlock::const_iterator I, E = B->getFirstNonPHI();
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for (I = B->begin(); I != E; ++I) {
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const MachineOperand &RO1 = I->getOperand(1);
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const MachineOperand &RO3 = I->getOperand(3);
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assert(RO1.isReg() && RO3.isReg());
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for (const MachineInstr &MI : *B) {
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if (!MI.isPHI())
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break;
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// If both incoming blocks are one of the TrueB/FalseB/SplitB, then
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// a MUX may be needed. Otherwise the PHI will need to be updated at
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// no extra cost.
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// Find the interesting PHI operands for further checks.
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SmallVector<unsigned,2> Inc;
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for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
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const MachineBasicBlock *BB = MI.getOperand(i+1).getMBB();
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if (BB == FP.SplitB || BB == FP.TrueB || BB == FP.FalseB)
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Inc.push_back(i);
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}
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assert(Inc.size() <= 2);
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if (Inc.size() < 2)
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continue;
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const MachineOperand &RA = MI.getOperand(1);
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const MachineOperand &RB = MI.getOperand(3);
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assert(RA.isReg() && RB.isReg());
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// Must have a MUX if the phi uses a subregister.
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if (RO1.getSubReg() != 0 || RO3.getSubReg() != 0) {
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if (RA.getSubReg() != 0 || RA.getSubReg() != 0) {
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Cost++;
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continue;
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}
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MachineInstr *Def1 = MRI->getVRegDef(RO1.getReg());
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MachineInstr *Def3 = MRI->getVRegDef(RO3.getReg());
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const MachineInstr *Def1 = MRI->getVRegDef(RA.getReg());
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const MachineInstr *Def3 = MRI->getVRegDef(RB.getReg());
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if (!HII->isPredicable(*Def1) || !HII->isPredicable(*Def3))
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Cost++;
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}
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@ -491,7 +513,6 @@ unsigned HexagonEarlyIfConversion::countPredicateDefs(
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bool HexagonEarlyIfConversion::isProfitable(const FlowPattern &FP) const {
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if (FP.TrueB && FP.FalseB) {
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// Do not IfCovert if the branch is one sided.
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if (MBPI) {
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BranchProbability Prob(9, 10);
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@ -542,17 +563,17 @@ bool HexagonEarlyIfConversion::isProfitable(const FlowPattern &FP) const {
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unsigned TotalPh = 0;
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unsigned PredDefs = countPredicateDefs(FP.SplitB);
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if (FP.JoinB) {
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TotalPh = computePhiCost(FP.JoinB);
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TotalPh = computePhiCost(FP.JoinB, FP);
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PredDefs += countPredicateDefs(FP.JoinB);
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} else {
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if (FP.TrueB && FP.TrueB->succ_size() > 0) {
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MachineBasicBlock *SB = *FP.TrueB->succ_begin();
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TotalPh += computePhiCost(SB);
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TotalPh += computePhiCost(SB, FP);
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PredDefs += countPredicateDefs(SB);
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}
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if (FP.FalseB && FP.FalseB->succ_size() > 0) {
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MachineBasicBlock *SB = *FP.FalseB->succ_begin();
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TotalPh += computePhiCost(SB);
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TotalPh += computePhiCost(SB, FP);
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PredDefs += countPredicateDefs(SB);
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}
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}
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@ -739,6 +760,43 @@ void HexagonEarlyIfConversion::predicateBlockNB(MachineBasicBlock *ToB,
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}
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}
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unsigned HexagonEarlyIfConversion::buildMux(MachineBasicBlock *B,
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MachineBasicBlock::iterator At, const TargetRegisterClass *DRC,
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unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) {
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unsigned Opc = 0;
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switch (DRC->getID()) {
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case Hexagon::IntRegsRegClassID:
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Opc = Hexagon::C2_mux;
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break;
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case Hexagon::DoubleRegsRegClassID:
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Opc = Hexagon::PS_pselect;
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break;
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case Hexagon::VectorRegsRegClassID:
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Opc = Hexagon::PS_vselect;
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break;
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case Hexagon::VecDblRegsRegClassID:
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Opc = Hexagon::PS_wselect;
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break;
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case Hexagon::VectorRegs128BRegClassID:
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Opc = Hexagon::PS_vselect_128B;
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break;
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case Hexagon::VecDblRegs128BRegClassID:
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Opc = Hexagon::PS_wselect_128B;
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break;
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default:
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llvm_unreachable("unexpected register type");
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}
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const MCInstrDesc &D = HII->get(Opc);
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DebugLoc DL = B->findBranchDebugLoc();
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unsigned MuxR = MRI->createVirtualRegister(DRC);
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BuildMI(*B, At, DL, D, MuxR)
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.addReg(PredR)
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.addReg(TR, 0, TSR)
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.addReg(FR, 0, FSR);
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return MuxR;
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}
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void HexagonEarlyIfConversion::updatePhiNodes(MachineBasicBlock *WhereB,
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const FlowPattern &FP) {
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// Visit all PHI nodes in the WhereB block and generate MUX instructions
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@ -765,40 +823,25 @@ void HexagonEarlyIfConversion::updatePhiNodes(MachineBasicBlock *WhereB,
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TR = SR, TSR = SSR;
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else if (FR == 0)
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FR = SR, FSR = SSR;
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assert(TR && FR);
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using namespace Hexagon;
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assert(TR || FR);
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unsigned MuxR = 0, MuxSR = 0;
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if (TR && FR) {
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unsigned DR = PN->getOperand(0).getReg();
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const TargetRegisterClass *RC = MRI->getRegClass(DR);
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unsigned Opc = 0;
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if (RC == &IntRegsRegClass)
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Opc = C2_mux;
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else if (RC == &DoubleRegsRegClass)
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Opc = PS_pselect;
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else if (RC == &VectorRegsRegClass)
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Opc = PS_vselect;
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else if (RC == &VecDblRegsRegClass)
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Opc = PS_wselect;
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else if (RC == &VectorRegs128BRegClass)
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Opc = PS_vselect_128B;
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else if (RC == &VecDblRegs128BRegClass)
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Opc = PS_wselect_128B;
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else
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llvm_unreachable("unexpected register type");
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const MCInstrDesc &D = HII->get(Opc);
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MuxR = buildMux(FP.SplitB, FP.SplitB->getFirstTerminator(), RC,
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FP.PredR, TR, TSR, FR, FSR);
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} else if (TR) {
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MuxR = TR;
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MuxSR = TSR;
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} else {
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MuxR = FR;
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MuxSR = FSR;
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}
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MachineBasicBlock::iterator MuxAt = FP.SplitB->getFirstTerminator();
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DebugLoc DL;
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if (MuxAt != FP.SplitB->end())
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DL = MuxAt->getDebugLoc();
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unsigned MuxR = MRI->createVirtualRegister(RC);
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BuildMI(*FP.SplitB, MuxAt, DL, D, MuxR)
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.addReg(FP.PredR)
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.addReg(TR, 0, TSR)
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.addReg(FR, 0, FSR);
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PN->addOperand(MachineOperand::CreateReg(MuxR, false));
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PN->addOperand(MachineOperand::CreateReg(MuxR, false, false, false, false,
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false, false, MuxSR));
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PN->addOperand(MachineOperand::CreateMBB(FP.SplitB));
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}
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}
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@ -2,7 +2,7 @@
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; CHECK: .LJTI
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; CHECK-DAG: r[[REG:[0-9]+]] = memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+<<#[0-9]+}})
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; CHECK-DAG: jumpr:nt r[[REG]]
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; CHECK-DAG: jumpr r[[REG]]
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define void @main() #0 {
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entry:
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@ -0,0 +1,91 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Make sure that the loop in the end has only one basic block.
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; CHECK-LABEL: fred
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; Rely on the comments, make sure the one for the loop header is present.
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; CHECK: %loop
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; CHECK-NOT: %should_merge
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target triple = "hexagon"
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define i32 @fred(i32 %a0, i64* nocapture readonly %a1) #0 {
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b2:
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%v3 = bitcast i64* %a1 to i32*
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%v4 = getelementptr inbounds i32, i32* %v3, i32 1
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%v5 = zext i32 %a0 to i64
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br label %loop
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loop: ; preds = %should_merge, %b2
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%v7 = phi i32 [ 0, %b2 ], [ %v49, %should_merge ]
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%v8 = phi i32 [ 0, %b2 ], [ %v42, %should_merge ]
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%v9 = phi i32* [ %v4, %b2 ], [ %v53, %should_merge ]
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%v10 = phi i32 [ 0, %b2 ], [ %v30, %should_merge ]
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%v11 = phi i32* [ %v3, %b2 ], [ %v51, %should_merge ]
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%v12 = phi i32 [ 0, %b2 ], [ %v23, %should_merge ]
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%v13 = phi i32 [ 2, %b2 ], [ %v54, %should_merge ]
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%v14 = load i32, i32* %v11, align 4, !tbaa !0
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%v15 = load i32, i32* %v9, align 4, !tbaa !0
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%v16 = icmp ult i32 %v13, 30
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%v17 = zext i32 %v12 to i64
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%v18 = shl nuw i64 %v17, 32
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%v19 = zext i32 %v14 to i64
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%v20 = or i64 %v18, %v19
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%v21 = tail call i64 @llvm.hexagon.A2.addp(i64 %v20, i64 %v5)
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%v22 = lshr i64 %v21, 32
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%v23 = trunc i64 %v22 to i32
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%v24 = zext i32 %v10 to i64
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%v25 = shl nuw i64 %v24, 32
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%v26 = zext i32 %v15 to i64
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%v27 = or i64 %v25, %v26
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%v28 = tail call i64 @llvm.hexagon.A2.addp(i64 %v27, i64 %v5)
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%v29 = lshr i64 %v28, 32
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%v30 = trunc i64 %v29 to i32
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%v31 = getelementptr inbounds i32, i32* %v3, i32 %v13
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%v32 = load i32, i32* %v31, align 4, !tbaa !0
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%v33 = or i32 %v13, 1
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%v34 = getelementptr inbounds i32, i32* %v3, i32 %v33
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%v35 = load i32, i32* %v34, align 4, !tbaa !0
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%v36 = zext i32 %v8 to i64
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%v37 = shl nuw i64 %v36, 32
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%v38 = zext i32 %v32 to i64
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%v39 = or i64 %v37, %v38
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%v40 = tail call i64 @llvm.hexagon.A2.subp(i64 %v39, i64 %v5)
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%v41 = lshr i64 %v40, 32
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%v42 = trunc i64 %v41 to i32
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%v43 = zext i32 %v7 to i64
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%v44 = shl nuw i64 %v43, 32
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%v45 = zext i32 %v35 to i64
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%v46 = or i64 %v44, %v45
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%v47 = tail call i64 @llvm.hexagon.A2.subp(i64 %v46, i64 %v5)
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%v48 = lshr i64 %v47, 32
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%v49 = trunc i64 %v48 to i32
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br i1 %v16, label %should_merge, label %exit
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should_merge: ; preds = %loop
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%v50 = add nuw nsw i32 %v13, 2
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%v51 = getelementptr inbounds i32, i32* %v3, i32 %v50
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%v52 = add nuw nsw i32 %v13, 3
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%v53 = getelementptr inbounds i32, i32* %v3, i32 %v52
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%v54 = add nuw nsw i32 %v13, 4
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br label %loop
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exit: ; preds = %loop
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%v57 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v42, i32 %v23)
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%v58 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v49, i32 %v30)
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%v59 = tail call i64 @llvm.hexagon.A2.addp(i64 %v57, i64 %v58)
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%v60 = lshr i64 %v59, 32
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%v61 = trunc i64 %v60 to i32
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ret i32 %v61
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}
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declare i64 @llvm.hexagon.A2.addp(i64, i64) #1
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declare i64 @llvm.hexagon.A2.subp(i64, i64) #1
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declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
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attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }
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attributes #1 = { nounwind readnone }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"long", !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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