Fix null reference creation in ScheduleDAGInstrs constructor call.
Both MachineLoopInfo and MachineDominatorTree may be null in ScheduleDAGMI constructor call. It is undefined behavior to take references to these values. This bug is reported by UBSan. llvm-svn: 216118
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@ -250,7 +250,7 @@ protected:
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public:
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public:
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ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S,
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ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S,
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bool IsPostRA)
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bool IsPostRA)
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: ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, IsPostRA,
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: ScheduleDAGInstrs(*C->MF, C->MLI, C->MDT, IsPostRA,
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/*RemoveKillFlags=*/IsPostRA, C->LIS),
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/*RemoveKillFlags=*/IsPostRA, C->LIS),
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AA(C->AA), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU), CurrentTop(),
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AA(C->AA), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU), CurrentTop(),
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CurrentBottom(), NextClusterPred(nullptr), NextClusterSucc(nullptr) {
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CurrentBottom(), NextClusterPred(nullptr), NextClusterSucc(nullptr) {
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@ -75,8 +75,8 @@ namespace llvm {
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/// MachineInstrs.
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/// MachineInstrs.
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class ScheduleDAGInstrs : public ScheduleDAG {
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class ScheduleDAGInstrs : public ScheduleDAG {
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protected:
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protected:
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const MachineLoopInfo &MLI;
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const MachineLoopInfo *MLI;
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const MachineDominatorTree &MDT;
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const MachineDominatorTree *MDT;
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const MachineFrameInfo *MFI;
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const MachineFrameInfo *MFI;
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/// Live Intervals provides reaching defs in preRA scheduling.
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/// Live Intervals provides reaching defs in preRA scheduling.
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@ -154,8 +154,8 @@ namespace llvm {
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public:
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public:
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explicit ScheduleDAGInstrs(MachineFunction &mf,
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explicit ScheduleDAGInstrs(MachineFunction &mf,
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const MachineLoopInfo &mli,
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const MachineLoopInfo *mli,
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const MachineDominatorTree &mdt,
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const MachineDominatorTree *mdt,
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bool IsPostRAFlag,
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bool IsPostRAFlag,
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bool RemoveKillFlags = false,
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bool RemoveKillFlags = false,
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LiveIntervals *LIS = nullptr);
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LiveIntervals *LIS = nullptr);
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@ -115,7 +115,7 @@ public:
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DefaultVLIWScheduler::DefaultVLIWScheduler(
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DefaultVLIWScheduler::DefaultVLIWScheduler(
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MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
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MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
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bool IsPostRA) :
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bool IsPostRA) :
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ScheduleDAGInstrs(MF, MLI, MDT, IsPostRA) {
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ScheduleDAGInstrs(MF, &MLI, &MDT, IsPostRA) {
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CanHandleTerminators = true;
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CanHandleTerminators = true;
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}
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}
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@ -197,7 +197,7 @@ SchedulePostRATDList::SchedulePostRATDList(
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AliasAnalysis *AA, const RegisterClassInfo &RCI,
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AliasAnalysis *AA, const RegisterClassInfo &RCI,
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TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
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TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
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SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs)
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SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs)
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: ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), AA(AA), EndIndex(0) {
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: ScheduleDAGInstrs(MF, &MLI, &MDT, /*IsPostRA=*/true), AA(AA), EndIndex(0) {
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const TargetMachine &TM = MF.getTarget();
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const TargetMachine &TM = MF.getTarget();
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const InstrItineraryData *InstrItins =
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const InstrItineraryData *InstrItins =
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@ -50,8 +50,8 @@ static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
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cl::init(true), cl::desc("Enable use of TBAA during MI GAD construction"));
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cl::init(true), cl::desc("Enable use of TBAA during MI GAD construction"));
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ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
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ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
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const MachineLoopInfo &mli,
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const MachineLoopInfo *mli,
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const MachineDominatorTree &mdt,
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const MachineDominatorTree *mdt,
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bool IsPostRAFlag,
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bool IsPostRAFlag,
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bool RemoveKillFlags,
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bool RemoveKillFlags,
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LiveIntervals *lis)
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LiveIntervals *lis)
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@ -145,7 +145,7 @@ void VLIWMachineScheduler::schedule() {
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<< "********** MI Converging Scheduling VLIW BB#" << BB->getNumber()
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<< "********** MI Converging Scheduling VLIW BB#" << BB->getNumber()
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<< " " << BB->getName()
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<< " " << BB->getName()
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<< " in_func " << BB->getParent()->getFunction()->getName()
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<< " in_func " << BB->getParent()->getFunction()->getName()
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<< " at loop depth " << MLI.getLoopDepth(BB)
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<< " at loop depth " << MLI->getLoopDepth(BB)
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<< " \n");
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<< " \n");
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buildDAGWithRegPressure();
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buildDAGWithRegPressure();
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