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llvm-svn: 33633
This commit is contained in:
Evan Cheng 2007-01-29 22:23:02 +00:00
parent 43e8518d8b
commit 8953edc8a5
1 changed files with 1 additions and 1 deletions
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llvm/lib/Target/ARM/ARMRegisterInfo.td
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@ -97,7 +97,7 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
}];
// FIXME: We are reserving r12 in case the PEI needs to use it to
// generate large stack offset. Make it available once we have register
// scavenging.
// scavenging. Similarly r3 is reserved in Thumb mode for now.
let MethodBodies = [{
// FP is R11, R9 is available.
static const unsigned ARM_GPR_AO_1[] = {