[ARM] create new pseudo t2LDRLIT_ga_pcrel for stack guards
We can't use the existing pseudo ARM::tLDRLIT_ga_pcrel for loading the stack guard for PIC code that references the GOT, since arm-pseudo may expand this to the narrow tLDRpci rather than the wider t2LDRpci. Create a new pseudo, t2LDRLIT_ga_pcrel, and expand it to t2LDRpci. Fixes: https://bugs.chromium.org/p/chromium/issues/detail?id=1270361 Reviewed By: ardb Differential Revision: https://reviews.llvm.org/D114762
This commit is contained in:
Nick Desaulniers
Ard Biesheuvel
parent
5bbe50148f
commit
89453ed6f2
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@ -1857,15 +1857,11 @@ bool ARMBaseInstrInfo::produceSameValue(const MachineInstr &MI0,
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const MachineInstr &MI1,
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const MachineRegisterInfo *MRI) const {
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unsigned Opcode = MI0.getOpcode();
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if (Opcode == ARM::t2LDRpci ||
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Opcode == ARM::t2LDRpci_pic ||
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Opcode == ARM::tLDRpci ||
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Opcode == ARM::tLDRpci_pic ||
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Opcode == ARM::LDRLIT_ga_pcrel ||
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Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
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Opcode == ARM::tLDRLIT_ga_pcrel ||
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Opcode == ARM::MOV_ga_pcrel ||
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Opcode == ARM::MOV_ga_pcrel_ldr ||
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if (Opcode == ARM::t2LDRpci || Opcode == ARM::t2LDRpci_pic ||
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Opcode == ARM::tLDRpci || Opcode == ARM::tLDRpci_pic ||
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Opcode == ARM::LDRLIT_ga_pcrel || Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
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Opcode == ARM::tLDRLIT_ga_pcrel || Opcode == ARM::t2LDRLIT_ga_pcrel ||
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Opcode == ARM::MOV_ga_pcrel || Opcode == ARM::MOV_ga_pcrel_ldr ||
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Opcode == ARM::t2MOV_ga_pcrel) {
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if (MI1.getOpcode() != Opcode)
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return false;
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@ -1877,11 +1873,9 @@ bool ARMBaseInstrInfo::produceSameValue(const MachineInstr &MI0,
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if (MO0.getOffset() != MO1.getOffset())
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return false;
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if (Opcode == ARM::LDRLIT_ga_pcrel ||
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Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
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Opcode == ARM::tLDRLIT_ga_pcrel ||
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Opcode == ARM::MOV_ga_pcrel ||
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Opcode == ARM::MOV_ga_pcrel_ldr ||
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if (Opcode == ARM::LDRLIT_ga_pcrel || Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
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Opcode == ARM::tLDRLIT_ga_pcrel || Opcode == ARM::t2LDRLIT_ga_pcrel ||
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Opcode == ARM::MOV_ga_pcrel || Opcode == ARM::MOV_ga_pcrel_ldr ||
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Opcode == ARM::t2MOV_ga_pcrel)
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// Ignore the PC labels.
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return MO0.getGlobal() == MO1.getGlobal();
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@ -2523,17 +2523,21 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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case ARM::LDRLIT_ga_pcrel:
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case ARM::LDRLIT_ga_pcrel_ldr:
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case ARM::tLDRLIT_ga_abs:
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case ARM::t2LDRLIT_ga_pcrel:
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case ARM::tLDRLIT_ga_pcrel: {
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Register DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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const MachineOperand &MO1 = MI.getOperand(1);
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auto Flags = MO1.getTargetFlags();
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const GlobalValue *GV = MO1.getGlobal();
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bool IsARM =
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Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
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bool IsARM = Opcode != ARM::tLDRLIT_ga_pcrel &&
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Opcode != ARM::tLDRLIT_ga_abs &&
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Opcode != ARM::t2LDRLIT_ga_pcrel;
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bool IsPIC =
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Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
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unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
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if (Opcode == ARM::t2LDRLIT_ga_pcrel)
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LDRLITOpc = ARM::t2LDRpci;
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unsigned PICAddOpc =
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IsARM
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? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
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@ -4250,6 +4250,19 @@ def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
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def : T2Pat<(ARMWrapperJT tjumptable:$dst), (t2LEApcrelJT tjumptable:$dst)>;
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let hasNoSchedulingInfo = 1 in {
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def t2LDRLIT_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
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IIC_iLoadiALU,
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[(set rGPR:$dst,
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(ARMWrapperPIC tglobaladdr:$addr))]>,
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Requires<[IsThumb, HasV8MBaseline, DontUseMovtInPic]>;
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}
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// TLS globals
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def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr),
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(t2LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>,
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Requires<[IsThumb, HasV8MBaseline, DontUseMovtInPic]>;
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// Pseudo instruction that combines ldr from constpool and add pc. This should
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// be expanded into two instructions late to allow if-conversion and
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// scheduling.
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@ -261,7 +261,7 @@ void Thumb2InstrInfo::expandLoadStackGuard(
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cast<GlobalValue>((*MI->memoperands_begin())->getValue());
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if (MF.getSubtarget<ARMSubtarget>().isGVInGOT(GV))
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expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_pcrel, ARM::t2LDRi12);
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expandLoadStackGuardBase(MI, ARM::t2LDRLIT_ga_pcrel, ARM::t2LDRi12);
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else if (MF.getTarget().isPositionIndependent())
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expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12);
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else
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@ -0,0 +1,32 @@
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; RUN: llc -filetype=obj -relocation-model=pic %s --verify-machineinstrs -print-after=postrapseudos 2>&1 | FileCheck -check-prefix=CHECK-POST-RA %s
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; RUN: llc -filetype=obj -relocation-model=pic %s --verify-machineinstrs -print-after=arm-pseudo 2>&1 | FileCheck -check-prefix=CHECK-POST-AP %s
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; CHECK-POST-RA: $r12 = t2LDRLIT_ga_pcrel target-flags(arm-got) @__stack_chk_guard
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; CHECK-POST-AP: $r12 = t2LDRpci %const.0, 14, $noreg
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target triple = "thumbv7-unknown-linux-android23"
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%"class.v8::internal::Assembler" = type {}
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%"class.v8::internal::Operand" = type { %"class.v8::internal::Register", %"class.v8::internal::Register", i32, i32, %"union.v8::internal::Operand::Value" }
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%"class.v8::internal::Register" = type {}
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%"union.v8::internal::Operand::Value" = type { i32, [20 x i8] }
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%"class.v8::internal::wasm::LiftoffAssembler" = type {}
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declare void @_ZN2v88internal9Assembler3addENS0_8RegisterES2_RKNS0_7OperandENS0_4SBitENS0_9ConditionE(%"class.v8::internal::Assembler"*, [1 x i32], [1 x i32], %"class.v8::internal::Operand"*, i32, i32)
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; Function Attrs: ssp
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define void @_ZN2v88internal4wasm16LiftoffAssembler13emit_i32_addiENS0_8RegisterES3_i(%"class.v8::internal::wasm::LiftoffAssembler"* %0, [1 x i32] %1, [1 x i32] %2, i32 %3) #0 {
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%5 = alloca %"class.v8::internal::Operand", align 8
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%6 = bitcast %"class.v8::internal::wasm::LiftoffAssembler"* %0 to %"class.v8::internal::Assembler"*
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%7 = bitcast %"class.v8::internal::Operand"* %5 to i8*
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%8 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
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%9 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
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%10 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
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%11 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
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%12 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5, i32 0, i32 4, i32 0
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store i32 %3, i32* %12, align 4
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call void @_ZN2v88internal9Assembler3addENS0_8RegisterES2_RKNS0_7OperandENS0_4SBitENS0_9ConditionE(%"class.v8::internal::Assembler"* %6, [1 x i32] %1, [1 x i32] %2, %"class.v8::internal::Operand"* %5, i32 0, i32 2)
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ret void
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}
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attributes #0 = { ssp }
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