diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/atomic_load.ll b/llvm/test/CodeGen/Hexagon/intrinsics/atomic_load.ll
new file mode 100644
index 000000000000..9b245dfbb5a3
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/intrinsics/atomic_load.ll
@@ -0,0 +1,68 @@
+; RUN: sed -e "s/ORDER/unordered/" %s | llc -march=hexagon -disable-hexagon-amodeopt=0 | FileCheck %s
+; RUN: sed -e "s/ORDER/monotonic/" %s | llc -march=hexagon -disable-hexagon-amodeopt=0 | FileCheck %s
+; RUN: sed -e "s/ORDER/acquire/" %s | llc -march=hexagon -disable-hexagon-amodeopt=0 | FileCheck %s
+; RUN: sed -e "s/ORDER/seq_cst/" %s | llc -march=hexagon -disable-hexagon-amodeopt=0 | FileCheck %s
+
+%struct.Obj = type { [100 x i32] }
+
+@i8Src   = global i8 0,  align 1
+@i8Dest  = global i8 0,  align 1
+@i16Src  = global i16 0, align 2
+@i16Dest = global i16 0, align 2
+@i32Src  = global i32 0, align 4
+@i32Dest = global i32 0, align 4
+@i64Src  = global i64 0, align 8
+@i64Dest = global i64 0, align 8
+@ptrSrc  = global %struct.Obj* null, align 4
+@ptrDest = global %struct.Obj* null, align 4
+
+define void @load_i8() #0 {
+entry:
+  %i8Tmp = load atomic i8, i8* @i8Src ORDER, align 1
+  store i8 %i8Tmp, i8* @i8Dest, align 1
+  ret void
+}
+; CHECK-LABEL: load_i8:
+; CHECK: [[TMP_REG:r[0-9]+]] = memub(gp+#i8Src)
+; CHECK: memb(gp+#i8Dest) = [[TMP_REG]]
+
+define void @load_i16() #0 {
+entry:
+  %i16Tmp = load atomic i16, i16* @i16Src ORDER, align 2
+  store i16 %i16Tmp, i16* @i16Dest, align 2
+  ret void
+}
+; CHECK-LABEL: load_i16:
+; CHECK: [[TMP_REG:r[0-9]+]] = memuh(gp+#i16Src)
+; CHECK: memh(gp+#i16Dest) = [[TMP_REG]]
+
+define void @load_i32() #0 {
+entry:
+  %i32Tmp = load atomic i32, i32* @i32Src ORDER, align 4
+  store i32 %i32Tmp, i32* @i32Dest, align 4
+  ret void
+}
+; CHECK-LABEL: load_i32:
+; CHECK: [[TMP_REG:r[0-9]+]] = memw(gp+#i32Src)
+; CHECK: memw(gp+#i32Dest) = [[TMP_REG]]
+
+define void @load_i64() #0 {
+entry:
+  %i64Tmp = load atomic i64, i64* @i64Src ORDER, align 8
+  store i64 %i64Tmp, i64* @i64Dest, align 8
+  ret void
+}
+; CHECK-LABEL: load_i64:
+; CHECK: [[TMP_REG:r[0-9]+:[0-9]+]] = memd(gp+#i64Src)
+; CHECK: memd(gp+#i64Dest) = [[TMP_REG]]
+
+define void @load_ptr() #0 {
+entry:
+  %ptrTmp = load atomic i32, i32* bitcast (%struct.Obj** @ptrSrc to i32*) ORDER, align 4
+  store i32 %ptrTmp, i32* bitcast (%struct.Obj** @ptrDest to i32*), align 4
+  ret void
+}
+; CHECK-LABEL: load_ptr:
+; CHECK: [[TMP_REG:r[0-9]+]] = memw(gp+#ptrSrc)
+; CHECK: memw(gp+#ptrDest) = [[TMP_REG]]
+
diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll b/llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll
new file mode 100644
index 000000000000..23baa2de9c2d
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll
@@ -0,0 +1,87 @@
+; RUN: sed -e "s/ORDER/monotonic/" -e "s/BINARY_OP/add/" %s | llc -march=hexagon | FileCheck %s
+; RUN: sed -e "s/ORDER/acquire/"   -e "s/BINARY_OP/add/" %s | llc -march=hexagon | FileCheck %s
+; RUN: sed -e "s/ORDER/release/"   -e "s/BINARY_OP/add/" %s | llc -march=hexagon | FileCheck %s
+; RUN: sed -e "s/ORDER/acq_rel/"   -e "s/BINARY_OP/add/" %s | llc -march=hexagon | FileCheck %s
+; RUN: sed -e "s/ORDER/seq_cst/"   -e "s/BINARY_OP/add/" %s | llc -march=hexagon | FileCheck %s
+; RUN: sed -e "s/ORDER/monotonic/" -e "s/BINARY_OP/sub/" %s | llc -march=hexagon | FileCheck %s
+; RUN: sed -e "s/ORDER/acquire/"   -e "s/BINARY_OP/sub/" %s | llc -march=hexagon | FileCheck %s
+; RUN: sed -e "s/ORDER/release/"   -e "s/BINARY_OP/sub/" %s | llc -march=hexagon | FileCheck %s
+; RUN: sed -e "s/ORDER/acq_rel/"   -e "s/BINARY_OP/sub/" %s | llc -march=hexagon | FileCheck %s
+; RUN: sed -e "s/ORDER/seq_cst/"   -e "s/BINARY_OP/sub/" %s | llc -march=hexagon | FileCheck %s
+
+%struct.Obj = type { [100 x i32] }
+
+@i32First   = global i32 0, align 4
+@i32Second  = global i32 0, align 4
+@i32Result  = global i32 0, align 4
+@i64First   = global i64 0, align 8
+@i64Second  = global i64 0, align 8
+@i64Result  = global i64 0, align 8
+@ptrFirst   = global %struct.Obj* null, align 4
+@ptrSecond  = global %struct.Obj* null, align 4
+@ptrResult  = global %struct.Obj* null, align 4
+
+define void @atomicrmw_op_i32() #0 {
+BINARY_OP_entry:
+  %i32First = load i32, i32* @i32First, align 4
+  %i32Result = atomicrmw BINARY_OP i32* @i32Second, i32 %i32First ORDER
+  store i32 %i32Result, i32* @i32Result, align 4
+  ret void
+}
+; CHECK-LABEL: atomicrmw_op_i32:
+; CHECK: // %[[BINARY_OP:[a-z_]*]]_entry
+; CHECK-DAG: [[SECOND_ADDR:r[0-9]+]] = ##i32Second
+; CHECK-DAG: [[FIRST_VALUE:r[0-9]+]] = memw(gp+#i32First)
+
+; CHECK: [[FAIL_LABEL:\.LBB.*]]:
+
+; CHECK: [[LOCKED_READ_REG:r[0-9]+]] = memw_locked([[SECOND_ADDR]])
+; CHECK: [[RESULT_REG:r[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
+; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
+
+; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK-DAG: memw(gp+#i32Result) = [[LOCKED_READ_REG]]
+; CHECK-DAG: jumpr r31
+
+define void @atomicrmw_op_i64() #0 {
+entry:
+  %i64First = load i64, i64* @i64First, align 8
+  %i64Result = atomicrmw BINARY_OP i64* @i64Second, i64 %i64First ORDER
+  store i64 %i64Result, i64* @i64Result, align 8
+  ret void
+}
+; CHECK-LABEL: atomicrmw_op_i64:
+; CHECK-DAG: [[SECOND_ADDR:r[0-9]+]] = ##i64Second
+; CHECK-DAG: [[FIRST_VALUE:r[0-9]+:[0-9]+]] = memd(gp+#i64First)
+
+; CHECK: [[FAIL_LABEL:\.LBB.*]]:
+
+; CHECK-DAG: [[LOCKED_READ_REG:r[0-9]+:[0-9]+]] = memd_locked([[SECOND_ADDR]])
+; CHECK: [[RESULT_REG:r[0-9]+:[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
+; CHECK: memd_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
+
+; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK-DAG: memd(gp+#i64Result) = [[LOCKED_READ_REG]]
+; CHECK-DAG: jumpr r31
+
+define void @atomicrmw_op_ptr() #0 {
+entry:
+  %ptrFirst = load i32, i32* bitcast (%struct.Obj** @ptrFirst to i32*), align 4
+  %ptrResult = atomicrmw BINARY_OP i32* bitcast (%struct.Obj** @ptrSecond to i32*), i32 %ptrFirst ORDER
+  store i32 %ptrResult, i32* bitcast (%struct.Obj** @ptrResult to i32*), align 4
+  ret void
+}
+; CHECK-LABEL: atomicrmw_op_ptr:
+; CHECK-DAG: [[SECOND_ADDR:r[0-9]+]] = ##ptrSecond
+; CHECK-DAG: [[FIRST_VALUE:r[0-9]+]] = memw(gp+#ptrFirst)
+
+; CHECK: [[FAIL_LABEL:\.LBB.*]]:
+
+; CHECK-DAG: [[LOCKED_READ_REG:r[0-9]+]] = memw_locked([[SECOND_ADDR]])
+; CHECK: [[RESULT_REG:r[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
+; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
+
+; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK-DAG: memw(gp+#ptrResult) = [[LOCKED_READ_REG]]
+; CHECK-DAG: jumpr r31
+
diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/fence.ll b/llvm/test/CodeGen/Hexagon/intrinsics/fence.ll
new file mode 100644
index 000000000000..6a34f3e13646
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/intrinsics/fence.ll
@@ -0,0 +1,22 @@
+; RUN: sed -e "s/ORDER/acquire/" %s | llc -march=hexagon | FileCheck %s
+; RUN: sed -e "s/ORDER/release/" %s | llc -march=hexagon | FileCheck %s
+; RUN: sed -e "s/ORDER/acq_rel/" %s | llc -march=hexagon | FileCheck %s
+; RUN: sed -e "s/ORDER/seq_cst/" %s | llc -march=hexagon | FileCheck %s
+; RUN: sed -e 's/ORDER/syncscope("singlethread") acquire/' %s | llc -march=hexagon | FileCheck %s
+; RUN: sed -e 's/ORDER/syncscope("singlethread") release/' %s | llc -march=hexagon | FileCheck %s
+; RUN: sed -e 's/ORDER/syncscope("singlethread") acq_rel/' %s | llc -march=hexagon | FileCheck %s
+; RUN: sed -e 's/ORDER/syncscope("singlethread") seq_cst/' %s | llc -march=hexagon | FileCheck %s
+
+define void @fence_func() #0 {
+entry:
+  fence ORDER
+  ret void
+}
+; CHECK-LABEL: fence_func:
+; CHECK: %bb.0
+; CHECK-NEXT: {
+; CHECK-NEXT:   barrier
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT:   jumpr r31
+; CHECK-NEXT: }