Extract method for detecting constant unallocatable physregs.
It is safe to move uses of such registers. llvm-svn: 148259
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@ -64,6 +64,9 @@ class MachineRegisterInfo {
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/// started.
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/// started.
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BitVector ReservedRegs;
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BitVector ReservedRegs;
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/// AllocatableRegs - From TRI->getAllocatableSet.
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mutable BitVector AllocatableRegs;
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/// LiveIns/LiveOuts - Keep track of the physical registers that are
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/// LiveIns/LiveOuts - Keep track of the physical registers that are
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/// livein/liveout of the function. Live in values are typically arguments in
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/// livein/liveout of the function. Live in values are typically arguments in
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/// registers, live out values are typically return values in registers.
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/// registers, live out values are typically return values in registers.
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@ -216,6 +219,11 @@ public:
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void dumpUses(unsigned RegNo) const;
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void dumpUses(unsigned RegNo) const;
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#endif
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#endif
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/// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
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/// throughout the function. It is safe to move instructions that read such
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/// a physreg.
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bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
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//===--------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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// Virtual Register Info
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// Virtual Register Info
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//===--------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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@ -81,8 +81,6 @@ namespace {
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MachineLoop *CurLoop; // The current loop we are working on.
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MachineLoop *CurLoop; // The current loop we are working on.
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MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
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MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
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BitVector AllocatableSet;
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// Track 'estimated' register pressure.
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// Track 'estimated' register pressure.
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SmallSet<unsigned, 32> RegSeen;
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SmallSet<unsigned, 32> RegSeen;
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SmallVector<unsigned, 8> RegPressure;
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SmallVector<unsigned, 8> RegPressure;
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@ -331,7 +329,6 @@ bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
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MFI = MF.getFrameInfo();
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MFI = MF.getFrameInfo();
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MRI = &MF.getRegInfo();
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MRI = &MF.getRegInfo();
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InstrItins = TM->getInstrItineraryData();
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InstrItins = TM->getInstrItineraryData();
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AllocatableSet = TRI->getAllocatableSet(MF);
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if (PreRegAlloc) {
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if (PreRegAlloc) {
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// Estimate register pressure during pre-regalloc pass.
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// Estimate register pressure during pre-regalloc pass.
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@ -905,18 +902,8 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
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// If the physreg has no defs anywhere, it's just an ambient register
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// If the physreg has no defs anywhere, it's just an ambient register
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// and we can freely move its uses. Alternatively, if it's allocatable,
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// and we can freely move its uses. Alternatively, if it's allocatable,
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// it could get allocated to something with a def during allocation.
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// it could get allocated to something with a def during allocation.
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if (!MRI->def_empty(Reg))
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if (!MRI->isConstantPhysReg(Reg, *I.getParent()->getParent()))
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return false;
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return false;
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if (AllocatableSet.test(Reg))
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return false;
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// Check for a def among the register's aliases too.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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if (!MRI->def_empty(AliasReg))
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return false;
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if (AllocatableSet.test(AliasReg))
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return false;
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}
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// Otherwise it's safe to move.
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// Otherwise it's safe to move.
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continue;
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continue;
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} else if (!MO.isDead()) {
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} else if (!MO.isDead()) {
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@ -263,3 +263,21 @@ void MachineRegisterInfo::dumpUses(unsigned Reg) const {
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void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
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void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
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ReservedRegs = TRI->getReservedRegs(MF);
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ReservedRegs = TRI->getReservedRegs(MF);
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}
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}
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bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
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const MachineFunction &MF) const {
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assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
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// Check if any overlapping register is modified.
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for (const unsigned *R = TRI->getOverlaps(PhysReg); *R; ++R)
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if (!def_empty(*R))
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return false;
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// Check if any overlapping register is allocatable so it may be used later.
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if (AllocatableRegs.empty())
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AllocatableRegs = TRI->getAllocatableSet(MF);
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for (const unsigned *R = TRI->getOverlaps(PhysReg); *R; ++R)
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if (AllocatableRegs.test(*R))
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return false;
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return true;
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}
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@ -485,21 +485,8 @@ MachineBasicBlock *MachineSinking::FindSuccToSinkTo(MachineInstr *MI,
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// If the physreg has no defs anywhere, it's just an ambient register
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// If the physreg has no defs anywhere, it's just an ambient register
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// and we can freely move its uses. Alternatively, if it's allocatable,
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// and we can freely move its uses. Alternatively, if it's allocatable,
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// it could get allocated to something with a def during allocation.
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// it could get allocated to something with a def during allocation.
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if (!MRI->def_empty(Reg))
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if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
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return NULL;
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return NULL;
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if (AllocatableSet.test(Reg))
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return NULL;
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// Check for a def among the register's aliases too.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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if (!MRI->def_empty(AliasReg))
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return NULL;
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if (AllocatableSet.test(AliasReg))
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return NULL;
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}
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} else if (!MO.isDead()) {
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} else if (!MO.isDead()) {
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// A def that isn't dead. We can't move it.
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// A def that isn't dead. We can't move it.
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return NULL;
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return NULL;
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@ -380,7 +380,6 @@ isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetMachine &TM = MF.getTarget();
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const TargetMachine &TM = MF.getTarget();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
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// Remat clients assume operand 0 is the defined register.
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// Remat clients assume operand 0 is the defined register.
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if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
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if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
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@ -432,19 +431,8 @@ isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
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// If the physreg has no defs anywhere, it's just an ambient register
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// If the physreg has no defs anywhere, it's just an ambient register
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// and we can freely move its uses. Alternatively, if it's allocatable,
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// and we can freely move its uses. Alternatively, if it's allocatable,
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// it could get allocated to something with a def during allocation.
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// it could get allocated to something with a def during allocation.
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if (!MRI.def_empty(Reg))
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if (!MRI.isConstantPhysReg(Reg, MF))
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return false;
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return false;
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BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0);
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if (AllocatableRegs.test(Reg))
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return false;
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// Check for a def among the register's aliases too.
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for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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if (!MRI.def_empty(AliasReg))
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return false;
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if (AllocatableRegs.test(AliasReg))
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return false;
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}
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} else {
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} else {
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// A physreg def. We can't remat it.
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// A physreg def. We can't remat it.
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return false;
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return false;
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