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[AArch64]Pattern match failures for truncate store and extend load 

llvm-svn: 196748
This commit is contained in:
Hao Liu 2013-12-09 03:34:08 +00:00
parent 34d6e9b371
commit 868caea6d1
2 changed files with 76 additions and 0 deletions
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19
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -368,6 +368,25 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
setOperationAction(ISD::FROUND, MVT::v4f32, Legal); setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
setOperationAction(ISD::FROUND, MVT::v1f64, Legal); setOperationAction(ISD::FROUND, MVT::v1f64, Legal);
setOperationAction(ISD::FROUND, MVT::v2f64, Legal); setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
// Vector ExtLoad and TruncStore are expanded.
for (unsigned I = MVT::FIRST_VECTOR_VALUETYPE;
I <= MVT::LAST_VECTOR_VALUETYPE; ++I) {
MVT VT = (MVT::SimpleValueType) I;
setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
setLoadExtAction(ISD::EXTLOAD, VT, Expand);
for (unsigned II = MVT::FIRST_VECTOR_VALUETYPE;
II <= MVT::LAST_VECTOR_VALUETYPE; ++II) {
MVT VT1 = (MVT::SimpleValueType) II;
// A TruncStore has two vector types of the same number of elements
// and different element sizes.
if (VT.getVectorNumElements() == VT1.getVectorNumElements() &&
VT.getVectorElementType().getSizeInBits()
> VT1.getVectorElementType().getSizeInBits())
setTruncStoreAction(VT, VT1, Expand);
}
}
} }
} }

57
llvm/test/CodeGen/AArch64/neon-truncStore-extLoad.ll Normal file
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@ -0,0 +1,57 @@
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
; A vector TruncStore can not be selected.
; Test a trunc IR and a vector store IR can be selected correctly.
define void @truncStore.v2i64(<2 x i64> %a, <2 x i32>* %result) {
; CHECK-LABEL: truncStore.v2i64:
; CHECK: xtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
; CHECK: st1 {v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}]
%b = trunc <2 x i64> %a to <2 x i32>
store <2 x i32> %b, <2 x i32>* %result
ret void
}
define void @truncStore.v4i32(<4 x i32> %a, <4 x i16>* %result) {
; CHECK-LABEL: truncStore.v4i32:
; CHECK: xtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
; CHECK: st1 {v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}]
%b = trunc <4 x i32> %a to <4 x i16>
store <4 x i16> %b, <4 x i16>* %result
ret void
}
define void @truncStore.v8i16(<8 x i16> %a, <8 x i8>* %result) {
; CHECK-LABEL: truncStore.v8i16:
; CHECK: xtn v{{[0-9]+}}.8b, v{{[0-9]+}}.8h
; CHECK: st1 {v{{[0-9]+}}.8b}, [x{{[0-9]+|sp}}]
%b = trunc <8 x i16> %a to <8 x i8>
store <8 x i8> %b, <8 x i8>* %result
ret void
}
; A vector LoadExt can not be selected.
; Test a vector load IR and a sext/zext IR can be selected correctly.
define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) {
; CHECK-LABEL: loadSExt.v4i8:
; CHECK: ldrsb
%a = load <4 x i8>* %ref
%conv = sext <4 x i8> %a to <4 x i32>
ret <4 x i32> %conv
}
define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) {
; CHECK-LABEL: loadZExt.v4i8:
; CHECK: ldrb
%a = load <4 x i8>* %ref
%conv = zext <4 x i8> %a to <4 x i32>
ret <4 x i32> %conv
}
define i32 @loadExt.i32(<4 x i8>* %ref) {
; CHECK-LABEL: loadExt.i32:
; CHECK: ldrb
%a = load <4 x i8>* %ref
%vecext = extractelement <4 x i8> %a, i32 0
%conv = zext i8 %vecext to i32
ret i32 %conv
}