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[AArch64][v8.5A] Add MTE as an optional AArch64 extension 

This adds the memory tagging extension, which is an optional extension
introduced in v8.5A. The new instructions and registers will be added by
subsequent patches.

Patch by Pablo Barrio!

Differential revision: https://reviews.llvm.org/D52486

llvm-svn: 343563
This commit is contained in:
Oliver Stannard 2018-10-02 09:36:28 +00:00
parent ad23f270db
commit 85de54090e
5 changed files with 9 additions and 1 deletions
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1
llvm/include/llvm/Support/AArch64TargetParser.def
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@ -71,6 +71,7 @@ AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras")
AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve")
AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc")
AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand")
AARCH64_ARCH_EXT_NAME("memtag", AArch64::AEK_MTE, "+mte", "-mte")
#undef AARCH64_ARCH_EXT_NAME
#ifndef AARCH64_CPU_NAME

1
llvm/include/llvm/Support/TargetParser.h
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@ -181,6 +181,7 @@ enum ArchExtKind : unsigned {
AEK_AES = 1 << 16,
AEK_FP16FML = 1 << 17,
AEK_RAND = 1 << 18,
AEK_MTE = 1 << 19,
};
StringRef getCanonicalArchName(StringRef Arch);

3
llvm/lib/Target/AArch64/AArch64.td
View File

@ -233,6 +233,9 @@ def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
"true", "Enable Random Number generation instructions" >;
def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
"true", "Enable Memory Tagging Extension" >;
//===----------------------------------------------------------------------===//
// Architectures.
//

2
llvm/lib/Target/AArch64/AArch64Subtarget.h
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@ -103,6 +103,7 @@ protected:
bool HasCCDP = false;
bool HasBTI = false;
bool HasRandGen = false;
bool HasMTE = false;
// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
bool HasZeroCycleRegMove = false;
@ -328,6 +329,7 @@ public:
bool hasCCDP() { return HasCCDP; }
bool hasBTI() { return HasBTI; }
bool hasRandGen() { return HasRandGen; }
bool hasMTE() { return HasMTE; }
bool isLittleEndian() const { return IsLittle; }

3
llvm/unittests/Support/TargetParserTest.cpp
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@ -966,7 +966,8 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"sve", "nosve", "+sve", "-sve"},
{"dotprod", "nodotprod", "+dotprod", "-dotprod"},
{"rcpc", "norcpc", "+rcpc", "-rcpc" },
{"rng", "norng", "+rand", "-rand"}};
{"rng", "norng", "+rand", "-rand"},
{"memtag", "nomemtag", "+mte", "-mte"}};
for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
EXPECT_EQ(StringRef(ArchExt[i][2]),