[ARM] Fix sema check of ARM special register names
Summary: This is a simple sema check patch for arguments of `__builtin_arm_rsr` and the related builtins, which currently do not allow special registers with indexes >7. Some of the possible register name formats these builtins accept are: ``` {c}p<coprocessor>:<op1>:c<CRn>:c<CRm>:<op2> ``` ``` o0:op1:CRn:CRm:op2 ``` where `op1` / `op2` are integers in the range [0, 7] and `CRn` / `CRm` are integers in the range [0, 15]. The current sema check does not allow `CRn` > 7 and accepts `op2` up to 15. Reviewers: LukeCheeseman, rengolin Subscribers: asl, aemerson, rengolin, cfe-commits Differential Revision: https://reviews.llvm.org/D26464 llvm-svn: 287378
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@ -4194,7 +4194,7 @@ bool Sema::SemaBuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall,
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SmallVector<int, 5> Ranges;
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if (FiveFields)
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Ranges.append({IsAArch64Builtin ? 1 : 15, 7, 7, 15, 15});
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Ranges.append({IsAArch64Builtin ? 1 : 15, 7, 15, 15, 7});
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else
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Ranges.append({15, 7, 15});
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@ -41,7 +41,7 @@ void wsr64_2(unsigned long v) {
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}
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unsigned rsr_2() {
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return __builtin_arm_rsr("0:1:2:3:4");
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return __builtin_arm_rsr("0:1:15:15:4");
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}
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void *rsrp_2() {
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@ -49,7 +49,7 @@ void *rsrp_2() {
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}
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unsigned long rsr64_2() {
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return __builtin_arm_rsr64("0:1:2:3:4");
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return __builtin_arm_rsr64("0:1:15:15:4");
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}
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void wsr_3(unsigned v) {
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@ -68,6 +68,18 @@ unsigned rsr_3() {
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return __builtin_arm_rsr("0:1:2"); //expected-error {{invalid special register for builtin}}
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}
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unsigned rsr_4() {
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return __builtin_arm_rsr("0:1:2:3:8"); //expected-error {{invalid special register for builtin}}
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}
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unsigned rsr_5() {
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return __builtin_arm_rsr("0:8:1:2:3"); //expected-error {{invalid special register for builtin}}
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}
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unsigned rsr_6() {
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return __builtin_arm_rsr("0:1:16:16:2"); //expected-error {{invalid special register for builtin}}
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}
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void *rsrp_3() {
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return __builtin_arm_rsrp("0:1:2"); //expected-error {{invalid special register for builtin}}
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}
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@ -75,3 +87,15 @@ void *rsrp_3() {
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unsigned long rsr64_3() {
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return __builtin_arm_rsr64("0:1:2"); //expected-error {{invalid special register for builtin}}
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}
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unsigned long rsr64_4() {
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return __builtin_arm_rsr64("0:1:2:3:8"); //expected-error {{invalid special register for builtin}}
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}
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unsigned long rsr64_5() {
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return __builtin_arm_rsr64("0:8:2:3:4"); //expected-error {{invalid special register for builtin}}
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}
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unsigned long rsr64_6() {
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return __builtin_arm_rsr64("0:1:16:16:2"); //expected-error {{invalid special register for builtin}}
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}
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@ -41,7 +41,7 @@ void wsr64_2(unsigned long v) {
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}
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unsigned rsr_2() {
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return __builtin_arm_rsr("cp0:1:c2:c3:4");
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return __builtin_arm_rsr("cp0:1:c15:c15:4");
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}
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void *rsrp_2() {
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@ -73,13 +73,25 @@ void *rsrp_3() {
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}
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unsigned long rsr64_3() {
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return __builtin_arm_rsr64("cp0:1:c2");
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return __builtin_arm_rsr64("cp0:1:c15");
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}
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unsigned rsr_4() {
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return __builtin_arm_rsr("0:1:2:3:4"); //expected-error {{invalid special register for builtin}}
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}
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unsigned rsr_5() {
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return __builtin_arm_rsr("cp0:1:c2:c3:8"); //expected-error {{invalid special register for builtin}}
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}
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unsigned rsr_6() {
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return __builtin_arm_rsr("cp0:8:c1:c2:3"); //expected-error {{invalid special register for builtin}}
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}
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unsigned rsr_7() {
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return __builtin_arm_rsr("cp0:1:c16:c16:2"); //expected-error {{invalid special register for builtin}}
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}
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void *rsrp_4() {
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return __builtin_arm_rsrp("0:1:2:3:4"); //expected-error {{invalid special register for builtin}}
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}
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@ -87,3 +99,11 @@ void *rsrp_4() {
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unsigned long rsr64_4() {
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return __builtin_arm_rsr64("0:1:2"); //expected-error {{invalid special register for builtin}}
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}
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unsigned long rsr64_5() {
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return __builtin_arm_rsr64("cp0:8:c1"); //expected-error {{invalid special register for builtin}}
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}
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unsigned long rsr64_6() {
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return __builtin_arm_rsr64("cp0:1:c16"); //expected-error {{invalid special register for builtin}}
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}
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