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[RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools 

Unfortunately these aren't defined explicitly in the privileged spec, but the
GNU assembler does accept `sfence.vma` and `sfence.vma rs` as well as the
usual `sfence.vma rs, rt`.

llvm-svn: 320575
This commit is contained in:
Alex Bradbury 2017-12-13 12:46:55 +00:00
parent acc90d17c5
commit 845e5dce83
3 changed files with 11 additions and 1 deletions
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3
llvm/lib/Target/RISCV/RISCVInstrInfo.td
View File

@ -459,6 +459,9 @@ def : InstAlias<"csrwi $csr, $imm", (CSRRWI X0, uimm12:$csr, uimm5:$imm)>;
def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, uimm12:$csr, uimm5:$imm)>;
def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, uimm12:$csr, uimm5:$imm)>;
def : InstAlias<"sfence.vma", (SFENCE_VMA X0, X0)>;
def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
//===----------------------------------------------------------------------===//
// Pseudo-instructions and codegen patterns
//

2
llvm/test/MC/RISCV/priv-invalid.s
View File

@ -2,6 +2,6 @@
mret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
sfence.vma zero # CHECK: :[[@LINE]]:1: error: too few operands for instruction
sfence.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
sfence.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction

7
llvm/test/MC/RISCV/rvi-aliases-valid.s
View File

@ -136,3 +136,10 @@ csrsi 0xfff, 0x10
# CHECK-INST: csrrci zero, 320, 17
# CHECK-ALIAS: csrci 320, 17
csrci 0x140, 0x11
# CHECK-INST: sfence.vma zero, zero
# CHECK-ALIAS: sfence.vma
sfence.vma
# CHECK-INST: sfence.vma a0, zero
# CHECK-ALIAS: sfence.vma a0
sfence.vma a0