[AArch64]Fix a problem that the register order of fmls/fmla by element is incorrect.
E.g. the codegen result is fmls v1.2s, v0.2s, v2.s[3] which is expected to be fmls v0.2s, v1.2s, v2.s[3] llvm-svn: 198001
This commit is contained in:
parent
6322e036aa
commit
83799741fb
|
@ -7258,7 +7258,7 @@ class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
|
|||
ValueType ResTy, ValueType OpTy,
|
||||
SDPatternOperator coreop>
|
||||
: Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
|
||||
(ResTy ResVPR:$src), (ResTy ResVPR:$Rn))),
|
||||
(ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
|
||||
(INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
|
||||
|
||||
// Pattern for lane 0
|
||||
|
|
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue