[Tests] Add LFTR tests for multiple exit loops (try 2)
(Recommit after fixing a keymash in the run line. Sorry for breakage.) This is preparation for D62625 <https://reviews.llvm.org/D62625> llvm-svn: 362426
This commit is contained in:
Philip Reames
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197a7c01e6
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -indvars -S | FileCheck %s
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; This is a collection of tests specifically for LFTR of multiple exit loops.
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; The actual LFTR performed is trivial so as to focus on the loop structure
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; aspects.
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; Provide legal integer types.
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target datalayout = "n8:16:32:64"
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@A = external global i32
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define void @analyzeable_early_exit(i32 %n) {
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; CHECK-LABEL: @analyzeable_early_exit(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[EARLYCND:%.*]] = icmp ult i32 [[IV]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[EARLYCND]], label [[LATCH]], label [[EXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: store i32 [[IV]], i32* @A
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[IV_NEXT]], 1000
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; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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%earlycnd = icmp ult i32 %iv, %n
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br i1 %earlycnd, label %latch, label %exit
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latch:
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%iv.next = add i32 %iv, 1
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store i32 %iv, i32* @A
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%c = icmp ult i32 %iv.next, 1000
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br i1 %c, label %loop, label %exit
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exit:
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ret void
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}
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define void @unanalyzeable_early_exit() {
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; CHECK-LABEL: @unanalyzeable_early_exit(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[VOL:%.*]] = load volatile i32, i32* @A
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; CHECK-NEXT: [[EARLYCND:%.*]] = icmp ne i32 [[VOL]], 0
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; CHECK-NEXT: br i1 [[EARLYCND]], label [[LATCH]], label [[EXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: store i32 [[IV]], i32* @A
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[IV_NEXT]], 1000
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; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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%vol = load volatile i32, i32* @A
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%earlycnd = icmp ne i32 %vol, 0
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br i1 %earlycnd, label %latch, label %exit
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latch:
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%iv.next = add i32 %iv, 1
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store i32 %iv, i32* @A
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%c = icmp ult i32 %iv.next, 1000
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br i1 %c, label %loop, label %exit
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exit:
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ret void
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}
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define void @multiple_early_exits(i32 %n, i32 %m) {
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; CHECK-LABEL: @multiple_early_exits(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[EARLYCND:%.*]] = icmp ult i32 [[IV]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[EARLYCND]], label [[CONTINUE:%.*]], label [[EXIT:%.*]]
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; CHECK: continue:
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; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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; CHECK-NEXT: [[EARLYCND2:%.*]] = icmp ult i32 [[IV]], [[M:%.*]]
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; CHECK-NEXT: br i1 [[EARLYCND2]], label [[LATCH]], label [[EXIT]]
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; CHECK: latch:
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[IV_NEXT]], 1000
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; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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%earlycnd = icmp ult i32 %iv, %n
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br i1 %earlycnd, label %continue, label %exit
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continue:
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store volatile i32 %iv, i32* @A
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%earlycnd2 = icmp ult i32 %iv, %m
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br i1 %earlycnd2, label %latch, label %exit
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latch:
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%iv.next = add i32 %iv, 1
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store volatile i32 %iv, i32* @A
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%c = icmp ult i32 %iv.next, 1000
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br i1 %c, label %loop, label %exit
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exit:
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ret void
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}
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; Note: This slightly odd form is what indvars itself produces for multiple
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; exits without a side effect between them.
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define void @compound_early_exit(i32 %n, i32 %m) {
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; CHECK-LABEL: @compound_early_exit(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[EARLYCND:%.*]] = icmp ult i32 [[IV]], [[N:%.*]]
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; CHECK-NEXT: [[EARLYCND2:%.*]] = icmp ult i32 [[IV]], [[M:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i1 [[EARLYCND]], [[EARLYCND2]]
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; CHECK-NEXT: br i1 [[AND]], label [[LATCH]], label [[EXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[IV_NEXT]], 1000
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; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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%earlycnd = icmp ult i32 %iv, %n
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%earlycnd2 = icmp ult i32 %iv, %m
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%and = and i1 %earlycnd, %earlycnd2
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br i1 %and, label %latch, label %exit
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latch:
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%iv.next = add i32 %iv, 1
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store volatile i32 %iv, i32* @A
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%c = icmp ult i32 %iv.next, 1000
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br i1 %c, label %loop, label %exit
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exit:
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ret void
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}
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define void @unanalyzeable_latch(i32 %n) {
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; CHECK-LABEL: @unanalyzeable_latch(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[EARLYCND:%.*]] = icmp ult i32 [[IV]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[EARLYCND]], label [[LATCH]], label [[EXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: store i32 [[IV]], i32* @A
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; CHECK-NEXT: [[VOL:%.*]] = load volatile i32, i32* @A
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[VOL]], 1000
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; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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%earlycnd = icmp ult i32 %iv, %n
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br i1 %earlycnd, label %latch, label %exit
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latch:
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%iv.next = add i32 %iv, 1
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store i32 %iv, i32* @A
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%vol = load volatile i32, i32* @A
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%c = icmp ult i32 %vol, 1000
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br i1 %c, label %loop, label %exit
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exit:
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ret void
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}
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define void @single_exit_no_latch(i32 %n) {
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; CHECK-LABEL: @single_exit_no_latch(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LATCH]], label [[EXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: store i32 [[IV]], i32* @A
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; CHECK-NEXT: br label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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%earlycnd = icmp ult i32 %iv, %n
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br i1 %earlycnd, label %latch, label %exit
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latch:
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%iv.next = add i32 %iv, 1
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store i32 %iv, i32* @A
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br label %loop
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exit:
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ret void
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}
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; Multiple exits which could be LFTRed, but the latch itself is not an
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; exiting block.
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define void @no_latch_exit(i32 %n, i32 %m) {
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; CHECK-LABEL: @no_latch_exit(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[EARLYCND:%.*]] = icmp ult i32 [[IV]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[EARLYCND]], label [[CONTINUE:%.*]], label [[EXIT:%.*]]
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; CHECK: continue:
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; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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; CHECK-NEXT: [[EARLYCND2:%.*]] = icmp ult i32 [[IV]], [[M:%.*]]
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; CHECK-NEXT: br i1 [[EARLYCND2]], label [[LATCH]], label [[EXIT]]
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; CHECK: latch:
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; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: br label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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%earlycnd = icmp ult i32 %iv, %n
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br i1 %earlycnd, label %continue, label %exit
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continue:
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store volatile i32 %iv, i32* @A
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%earlycnd2 = icmp ult i32 %iv, %m
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br i1 %earlycnd2, label %latch, label %exit
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latch:
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store volatile i32 %iv, i32* @A
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%iv.next = add i32 %iv, 1
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br label %loop
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exit:
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ret void
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}
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