diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
index a2b1e739bdc6..1e4b88f5b49e 100644
--- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
@@ -1636,19 +1636,6 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     }
     return Result;
     
-  case ISD::ZERO_EXTEND_INREG:
-    Tmp1 = SelectExpr(N.getOperand(0));
-    switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
-    default: Node->dump(); assert(0 && "Unhandled ZERO_EXTEND type"); break;
-    case MVT::i16:  Tmp2 = 16; break;
-    case MVT::i8:   Tmp2 = 24; break;
-    case MVT::i1:   Tmp2 = 31; break;
-    }
-    Opc = Recording ? PPC::RLWINMo : PPC::RLWINM;
-    RecordSuccess = true;
-    BuildMI(BB, Opc, 4, Result).addReg(Tmp1).addImm(0).addImm(Tmp2).addImm(31);
-    return Result;
-    
   case ISD::CopyFromReg:
     if (Result == 1)
       Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
diff --git a/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp
index 0d706f80f8fd..5604a9e8e54c 100644
--- a/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp
+++ b/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp
@@ -1154,18 +1154,6 @@ unsigned ISel::SelectExpr(SDOperand N) {
     }
     return Result;
     
-  case ISD::ZERO_EXTEND_INREG:
-    Tmp1 = SelectExpr(N.getOperand(0));
-    switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
-    default: Node->dump(); assert(0 && "Unhandled ZERO_EXTEND type"); break;
-    case MVT::i16:  Tmp2 = 16; break;
-    case MVT::i8:   Tmp2 = 24; break;
-    case MVT::i1:   Tmp2 = 31; break;
-    }
-    BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(0).addImm(Tmp2)
-      .addImm(31);
-    return Result;
-    
   case ISD::CopyFromReg:
     if (Result == 1)
       Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());