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Fix assembling ARM vst2 instructions with double-spaced registers. 

llvm-svn: 153099
This commit is contained in:
Kevin Enderby 2012-03-20 17:41:51 +00:00
parent 6e60c1376f
commit 816ca27ef6
3 changed files with 9 additions and 1 deletions
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2
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -1102,7 +1102,7 @@ public:
} }
bool isVecListDPairSpaced() const { bool isVecListDPairSpaced() const {
if (!isSingleSpacedVectorList()) return false; if (isSingleSpacedVectorList()) return false;
return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
.contains(VectorList.RegNum)); .contains(VectorList.RegNum));
} }

4
llvm/test/MC/ARM/neon-vst-encoding.s
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@ -264,3 +264,7 @@
@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4] @ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4]
@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4] @ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4]
@ CHECK: vst1.32 {d4, d5}, [r2] @ encoding: [0x8f,0x4a,0x02,0xf4] @ CHECK: vst1.32 {d4, d5}, [r2] @ encoding: [0x8f,0x4a,0x02,0xf4]
@ rdar://11082188
vst2.8 {d8, d10}, [r4]
@ CHECK: vst2.8 {d8, d10}, [r4] @ encoding: [0x0f,0x89,0x04,0xf4]

4
llvm/test/MC/ARM/neont2-vst-encoding.s
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@ -101,3 +101,7 @@
vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64]
@ CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf9] @ CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf9]
vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
@ rdar://11082188
vst2.8 {d8, d10}, [r4]
@ CHECK: vst2.8 {d8, d10}, [r4] @ encoding: [0x04,0xf9,0x0f,0x89]