[Hexagon] Avoid early if-conversion for one sided branches
Patch by Anand Kodnani. llvm-svn: 328344
This commit is contained in:
Krzysztof Parzyszek
parent
6c63e6c222
commit
80f10e4fe5
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@ -100,7 +100,7 @@ namespace llvm {
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} // end namespace llvm
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static cl::opt<bool> EnableHexagonBP("enable-hexagon-br-prob", cl::Hidden,
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cl::init(false), cl::desc("Enable branch probability info"));
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cl::init(true), cl::desc("Enable branch probability info"));
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static cl::opt<unsigned> SizeLimit("eif-limit", cl::init(6), cl::Hidden,
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cl::desc("Size limit in Hexagon early if-conversion"));
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static cl::opt<bool> SkipExitBranches("eif-no-loop-exit", cl::init(false),
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@ -243,7 +243,7 @@ bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B,
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// Interested only in conditional branches, no .new, no new-value, etc.
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// Check the terminators directly, it's easier than handling all responses
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// from AnalyzeBranch.
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// from analyzeBranch.
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MachineBasicBlock *TB = nullptr, *FB = nullptr;
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MachineBasicBlock::const_iterator T1I = B->getFirstTerminator();
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if (T1I == B->end())
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@ -336,7 +336,7 @@ bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B,
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return true;
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}
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// KLUDGE: HexagonInstrInfo::AnalyzeBranch won't work on a block that
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// KLUDGE: HexagonInstrInfo::analyzeBranch won't work on a block that
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// contains EH_LABEL.
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bool HexagonEarlyIfConversion::hasEHLabel(const MachineBasicBlock *B) const {
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for (auto &I : *B)
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@ -345,7 +345,7 @@ bool HexagonEarlyIfConversion::hasEHLabel(const MachineBasicBlock *B) const {
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return false;
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}
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// KLUDGE: HexagonInstrInfo::AnalyzeBranch may be unable to recognize
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// KLUDGE: HexagonInstrInfo::analyzeBranch may be unable to recognize
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// that a block can never fall-through.
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bool HexagonEarlyIfConversion::hasUncondBranch(const MachineBasicBlock *B)
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const {
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@ -495,7 +495,7 @@ unsigned HexagonEarlyIfConversion::countPredicateDefs(
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unsigned R = MO.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(R))
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continue;
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if (MRI->getRegClass(R) == &Hexagon::PredRegsRegClass)
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if (isPredicate(R))
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PredDefs++;
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}
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}
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@ -503,10 +503,21 @@ unsigned HexagonEarlyIfConversion::countPredicateDefs(
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}
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bool HexagonEarlyIfConversion::isProfitable(const FlowPattern &FP) const {
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BranchProbability JumpProb(1, 10);
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BranchProbability Prob(9, 10);
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if (MBPI && FP.TrueB && !FP.FalseB &&
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(MBPI->getEdgeProbability(FP.SplitB, FP.TrueB) < JumpProb ||
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MBPI->getEdgeProbability(FP.SplitB, FP.TrueB) > Prob))
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return false;
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if (MBPI && !FP.TrueB && FP.FalseB &&
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(MBPI->getEdgeProbability(FP.SplitB, FP.FalseB) < JumpProb ||
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MBPI->getEdgeProbability(FP.SplitB, FP.FalseB) > Prob))
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return false;
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if (FP.TrueB && FP.FalseB) {
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// Do not IfCovert if the branch is one sided.
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if (MBPI) {
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BranchProbability Prob(9, 10);
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if (MBPI->getEdgeProbability(FP.SplitB, FP.TrueB) > Prob)
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return false;
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if (MBPI->getEdgeProbability(FP.SplitB, FP.FalseB) > Prob)
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@ -1018,11 +1029,7 @@ void HexagonEarlyIfConversion::mergeBlocks(MachineBasicBlock *PredB,
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HII->removeBranch(*PredB);
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PredB->removeSuccessor(SuccB);
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PredB->splice(PredB->end(), SuccB, SuccB->begin(), SuccB->end());
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MachineBasicBlock::succ_iterator I, E = SuccB->succ_end();
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for (I = SuccB->succ_begin(); I != E; ++I)
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PredB->addSuccessor(*I);
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PredB->normalizeSuccProbs();
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replacePhiEdges(SuccB, PredB);
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PredB->transferSuccessorsAndUpdatePHIs(SuccB);
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removeBlock(SuccB);
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if (!TermOk)
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PredB->updateTerminator();
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@ -1044,7 +1051,7 @@ void HexagonEarlyIfConversion::simplifyFlowGraph(const FlowPattern &FP) {
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// By now, the split block has only one successor (SB), and SB has only
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// one predecessor. We can try to merge them. We will need to update ter-
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// minators in FP.Split+SB, and that requires working AnalyzeBranch, which
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// minators in FP.Split+SB, and that requires working analyzeBranch, which
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// fails on Hexagon for blocks that have EH_LABELs. However, if SB ends
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// with an unconditional branch, we won't need to touch the terminators.
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if (!hasEHLabel(SB) || hasUncondBranch(SB))
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@ -0,0 +1,80 @@
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; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
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; Rely on the comments generated by llc. Check that "if.then" was not predicated.
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; CHECK: b2
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; CHECK-NOT: if{{.*}}memd
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; CHECK: b5
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%s.0 = type { [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [3 x i32], [24 x i32], [8 x %s.1], [5 x i32] }
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%s.1 = type { i32, i32 }
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@g0 = global i64 0
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@g1 = global i32 0
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@g2 = global i32 0
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@g3 = global i8 0
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declare i32 @llvm.hexagon.S2.cl0(i32) #0
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declare i32 @llvm.hexagon.S2.setbit.r(i32, i32) #0
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declare i64 @llvm.hexagon.M2.vmpy2s.s0(i32, i32) #0
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declare i64 @llvm.hexagon.M2.vmac2s.s0(i64, i32, i32) #0
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declare i64 @llvm.hexagon.A2.vaddws(i64, i64) #0
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declare i64 @llvm.hexagon.A2.vsubws(i64, i64) #0
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declare i32 @llvm.hexagon.A4.modwrapu(i32, i32) #0
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define void @f0(i32 %a0, i64* %a1) #1 {
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b0:
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br label %b1
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b1: ; preds = %b5, %b0
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%v0 = phi i32 [ 0, %b0 ], [ %v26, %b5 ]
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%v1 = phi i32 [ 0, %b0 ], [ %v25, %b5 ]
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%v2 = load i32, i32* @g1, align 4
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%v3 = load i32, i32* @g2, align 8
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%v4 = and i32 %v3, %v2
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br label %b2
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b2: ; preds = %b4, %b1
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%v5 = phi i64 [ %v21, %b4 ], [ 0, %b1 ]
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%v6 = phi i64 [ %v22, %b4 ], [ 0, %b1 ]
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%v7 = phi i32 [ %v9, %b4 ], [ %v4, %b1 ]
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%v8 = tail call i32 @llvm.hexagon.S2.cl0(i32 %v7)
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%v9 = tail call i32 @llvm.hexagon.S2.setbit.r(i32 %v7, i32 %v8)
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%v10 = getelementptr [10 x %s.0], [10 x %s.0]* inttoptr (i32 -121502345 to [10 x %s.0]*), i32 0, i32 %v1
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%v11 = getelementptr %s.0, %s.0* %v10, i32 0, i32 12, i32 %v8
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%v12 = load i32, i32* %v11, align 4
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%v13 = tail call i64 @llvm.hexagon.M2.vmpy2s.s0(i32 %v12, i32 %v12)
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%v14 = getelementptr %s.0, %s.0* %v10, i32 0, i32 13, i32 %v8
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%v15 = load i32, i32* %v14, align 4
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%v16 = tail call i64 @llvm.hexagon.M2.vmac2s.s0(i64 %v13, i32 %v15, i32 %v15)
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%v17 = load i8, i8* @g3, align 1
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%v18 = and i8 %v17, 1
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%v19 = icmp eq i8 %v18, 0
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br i1 %v19, label %b3, label %b4, !prof !0
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b3: ; preds = %b2
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%v20 = tail call i64 @llvm.hexagon.A2.vaddws(i64 %v5, i64 %v16)
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store i64 %v20, i64* %a1, align 8
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br label %b4
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b4: ; preds = %b3, %b2
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%v21 = phi i64 [ %v20, %b3 ], [ %v5, %b2 ]
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%v22 = tail call i64 @llvm.hexagon.A2.vsubws(i64 %v6, i64 %v16)
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%v23 = icmp eq i32 %v9, 0
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br i1 %v23, label %b5, label %b2, !prof !1
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b5: ; preds = %b4
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%v24 = add i32 %v1, 1
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%v25 = tail call i32 @llvm.hexagon.A4.modwrapu(i32 %v24, i32 10) #0
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%v26 = add i32 %v0, 1
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%v27 = icmp eq i32 %v26, %a0
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br i1 %v27, label %b6, label %b1, !prof !1
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b6: ; preds = %b5
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store i64 %v16, i64* @g0, align 8
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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!0 = !{!"branch_weights", i32 99, i32 1}
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!1 = !{!"branch_weights", i32 10, i32 90}
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