Add support for the Sparc implementation-defined "ASR" registers.
(Note that register "Y" is essentially just ASR0). Also added some test cases for divide and multiply, which had none before. Differential Revision: http://reviews.llvm.org/D8670 llvm-svn: 237580
This commit is contained in:
James Y Knight
parent
0c553afe6a
commit
807563df22
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@ -124,6 +124,15 @@ public:
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Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
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Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
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static unsigned ASRRegs[32] = {
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SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
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SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
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SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
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SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
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SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
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SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
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SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
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SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
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/// SparcOperand - Instances of this class represent a parsed Sparc machine
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/// instruction.
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@ -136,7 +145,7 @@ public:
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rk_DoubleReg,
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rk_QuadReg,
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rk_CCReg,
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rk_Y
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rk_ASRReg
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};
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private:
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enum KindTy {
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@ -661,9 +670,6 @@ SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
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default:
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Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
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break;
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case Sparc::Y:
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Op = SparcOperand::CreateToken("%y", S);
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break;
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case Sparc::ICC:
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if (name == "xcc")
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@ -753,7 +759,15 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
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if (name.equals("y")) {
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RegNo = Sparc::Y;
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RegKind = SparcOperand::rk_Y;
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RegKind = SparcOperand::rk_ASRReg;
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return true;
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}
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if (name.substr(0, 3).equals_lower("asr")
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&& !name.substr(3).getAsInteger(10, intVal)
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&& intVal > 0 && intVal < 32) {
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RegNo = ASRRegs[intVal];
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RegKind = SparcOperand::rk_ASRReg;
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return true;
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}
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@ -107,6 +107,16 @@ static const unsigned QFPRegDecoderTable[] = {
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static const unsigned FCCRegDecoderTable[] = {
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SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
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static const unsigned ASRRegDecoderTable[] = {
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SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
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SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
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SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
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SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
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SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
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SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
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SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
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SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
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static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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@ -177,6 +187,15 @@ static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo]));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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@ -168,8 +168,10 @@ SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
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} else {
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TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
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}
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TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Glue, TopPart,
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CurDAG->getRegister(SP::G0, MVT::i32)), 0);
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TopPart = SDValue(CurDAG->getMachineNode(SP::WRASRrr, dl, MVT::i32,
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TopPart,
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CurDAG->getRegister(SP::G0, MVT::i32)), 0);
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TopPart = CurDAG->getCopyToReg(TopPart, dl, SP::Y, TopPart, SDValue()).getValue(1);
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// FIXME: Handle div by immediate.
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unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
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@ -185,7 +187,9 @@ SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
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SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
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MulLHS, MulRHS);
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// The high part is in the Y register.
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return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
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return CurDAG->SelectNodeTo(N, SP::RDASR, MVT::i32,
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CurDAG->getRegister(SP::Y, MVT::i32),
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SDValue(Mul, 1));
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}
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}
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@ -705,20 +705,19 @@ let Uses = [O6],
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}
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// Section B.28 - Read State Register Instructions
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let Uses = [Y], rs1 = 0, rs2 = 0 in
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def RDY : F3_1<2, 0b101000,
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(outs IntRegs:$dst), (ins),
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"rd %y, $dst", []>;
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let rs2 = 0 in
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def RDASR : F3_1<2, 0b101000,
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(outs IntRegs:$rd), (ins ASRRegs:$rs1),
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"rd $rs1, $rd", []>;
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// Section B.29 - Write State Register Instructions
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let Defs = [Y], rd = 0 in {
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def WRYrr : F3_1<2, 0b110000,
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(outs), (ins IntRegs:$rs1, IntRegs:$rs2),
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"wr $rs1, $rs2, %y", []>;
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def WRYri : F3_2<2, 0b110000,
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(outs), (ins IntRegs:$rs1, simm13Op:$simm13),
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"wr $rs1, $simm13, %y", []>;
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}
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def WRASRrr : F3_1<2, 0b110000,
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(outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
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"wr $rs1, $rs2, $rd", []>;
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def WRASRri : F3_2<2, 0b110000,
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(outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
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"wr $rs1, $simm13, $rd", []>;
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// Convert Integer to Floating-point Instructions, p. 141
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def FITOS : F3_3u<2, 0b110100, 0b011000100,
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(outs FPRegs:$rd), (ins FPRegs:$rs2),
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@ -56,6 +56,38 @@ foreach I = 0-3 in
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// Y register
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def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
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// Ancillary state registers (implementation defined)
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def ASR1 : SparcCtrlReg<1, "ASR1">;
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def ASR2 : SparcCtrlReg<2, "ASR2">;
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def ASR3 : SparcCtrlReg<3, "ASR3">;
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def ASR4 : SparcCtrlReg<4, "ASR4">;
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def ASR5 : SparcCtrlReg<5, "ASR5">;
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def ASR6 : SparcCtrlReg<6, "ASR6">;
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def ASR7 : SparcCtrlReg<7, "ASR7">;
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def ASR8 : SparcCtrlReg<8, "ASR8">;
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def ASR9 : SparcCtrlReg<9, "ASR9">;
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def ASR10 : SparcCtrlReg<10, "ASR10">;
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def ASR11 : SparcCtrlReg<11, "ASR11">;
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def ASR12 : SparcCtrlReg<12, "ASR12">;
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def ASR13 : SparcCtrlReg<13, "ASR13">;
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def ASR14 : SparcCtrlReg<14, "ASR14">;
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def ASR15 : SparcCtrlReg<15, "ASR15">;
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def ASR16 : SparcCtrlReg<16, "ASR16">;
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def ASR17 : SparcCtrlReg<17, "ASR17">;
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def ASR18 : SparcCtrlReg<18, "ASR18">;
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def ASR19 : SparcCtrlReg<19, "ASR19">;
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def ASR20 : SparcCtrlReg<20, "ASR20">;
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def ASR21 : SparcCtrlReg<21, "ASR21">;
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def ASR22 : SparcCtrlReg<22, "ASR22">;
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def ASR23 : SparcCtrlReg<23, "ASR23">;
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def ASR24 : SparcCtrlReg<24, "ASR24">;
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def ASR25 : SparcCtrlReg<25, "ASR25">;
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def ASR26 : SparcCtrlReg<26, "ASR26">;
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def ASR27 : SparcCtrlReg<27, "ASR27">;
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def ASR28 : SparcCtrlReg<28, "ASR28">;
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def ASR29 : SparcCtrlReg<29, "ASR29">;
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def ASR30 : SparcCtrlReg<30, "ASR30">;
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def ASR31 : SparcCtrlReg<31, "ASR31">;
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// Integer registers
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def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
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@ -209,3 +241,7 @@ def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>;
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// Floating point control register classes.
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def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;
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// Ancillary state registers
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def ASRRegs : RegisterClass<"SP", [i32], 32,
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(add Y, (sequence "ASR%u", 1, 31))>;
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@ -36,3 +36,51 @@ entry:
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ret i32 0
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}
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; CHECK-LABEL: signed_divide:
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; CHECK: sra %o0, 31, %o2
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; CHECK: wr %o2, %g0, %y
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; CHECK: sdiv %o0, %o1, %o0
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define i32 @signed_divide(i32 %a, i32 %b) {
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%r = sdiv i32 %a, %b
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ret i32 %r
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}
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; CHECK-LABEL: unsigned_divide:
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; CHECK: wr %g0, %g0, %y
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; CHECK: udiv %o0, %o1, %o0
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define i32 @unsigned_divide(i32 %a, i32 %b) {
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%r = udiv i32 %a, %b
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ret i32 %r
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}
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; CHECK-LABEL: multiply_32x32:
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; CHECK: smul %o0, %o1, %o0
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define i32 @multiply_32x32(i32 %a, i32 %b) {
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%r = mul i32 %a, %b
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ret i32 %r
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}
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; CHECK-LABEL: signed_multiply_32x32_64:
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; CHECK: smul %o0, %o1, %o1
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; CHECK: rd %y, %o0
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define i64 @signed_multiply_32x32_64(i32 %a, i32 %b) {
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%xa = sext i32 %a to i64
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%xb = sext i32 %b to i64
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%r = mul i64 %xa, %xb
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ret i64 %r
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}
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; CHECK-LABEL: unsigned_multiply_32x32_64:
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; CHECK: umul %o0, %o1, %o2
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; CHECK: rd %y, %o2
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;FIXME: the smul in the output is totally redundant and should not there.
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; CHECK: smul %o0, %o1, %o1
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; CHECK: retl
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; CHECK: mov %o2, %o0
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define i64 @unsigned_multiply_32x32_64(i32 %a, i32 %b) {
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%xa = zext i32 %a to i64
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%xb = zext i32 %b to i64
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%r = mul i64 %xa, %xb
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ret i64 %r
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}
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@ -200,3 +200,18 @@
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# CHECK: rett %i7+8
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0x81 0xcf 0xe0 0x08
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# CHECK: rd %y, %i0
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0xb1 0x40 0x00 0x00
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# CHECK: rd %asr1, %i0
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0xb1 0x40 0x40 0x00
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# CHECK: wr %i0, 5, %y
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0x81 0x86 0x20 0x05
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# CHECK: wr %i0, %i1, %asr15
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0x9f 0x86 0x00 0x19
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# CHECK: stbar
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0x81 0x43 0xc0 0x00
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@ -0,0 +1,17 @@
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! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s
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! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
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! CHECK: rd %y, %i0 ! encoding: [0xb1,0x40,0x00,0x00]
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rd %y, %i0
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! CHECK: rd %asr1, %i0 ! encoding: [0xb1,0x40,0x40,0x00]
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rd %asr1, %i0
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! CHECK: wr %i0, 5, %y ! encoding: [0x81,0x86,0x20,0x05]
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wr %i0, 5, %y
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! CHECK: wr %i0, %i1, %asr15 ! encoding: [0x9f,0x86,0x00,0x19]
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wr %i0, %i1, %asr15
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! CHECK: rd %asr15, %g0 ! encoding: [0x81,0x43,0xc0,0x00]
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rd %asr15, %g0
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