Annotate shifts and rotates with SchedRW lists.
llvm-svn: 177935
This commit is contained in:
Jakob Stoklund Olesen
parent
30b77bf737
commit
7fde8c4ef4
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@ -15,7 +15,7 @@
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let Defs = [EFLAGS] in {
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let Constraints = "$src1 = $dst" in {
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let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
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let Uses = [CL] in {
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def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
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"shl{b}\t{%cl, $dst|$dst, CL}",
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@ -62,9 +62,10 @@ def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
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"shl{q}\t$dst", [], IIC_SR>;
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} // hasSideEffects = 0
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} // isConvertibleToThreeAddress = 1
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} // Constraints = "$src = $dst"
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} // Constraints = "$src = $dst", SchedRW
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let SchedRW = [WriteShiftLd, WriteRMW] in {
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// FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern
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// using CL?
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let Uses = [CL] in {
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@ -118,8 +119,9 @@ def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
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"shl{q}\t$dst",
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[(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
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IIC_SR>;
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} // SchedRW
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let Constraints = "$src1 = $dst" in {
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let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
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let Uses = [CL] in {
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def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
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"shr{b}\t{%cl, $dst|$dst, CL}",
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@ -163,9 +165,10 @@ def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
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def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
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"shr{q}\t$dst",
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[(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;
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} // Constraints = "$src = $dst"
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} // Constraints = "$src = $dst", SchedRW
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let SchedRW = [WriteShiftLd, WriteRMW] in {
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let Uses = [CL] in {
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def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
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"shr{b}\t{%cl, $dst|$dst, CL}",
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@ -216,8 +219,9 @@ def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
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"shr{q}\t$dst",
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[(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
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IIC_SR>;
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} // SchedRW
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let Constraints = "$src1 = $dst" in {
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let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
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let Uses = [CL] in {
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def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
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"sar{b}\t{%cl, $dst|$dst, CL}",
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@ -273,9 +277,10 @@ def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
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"sar{q}\t$dst",
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[(set GR64:$dst, (sra GR64:$src1, (i8 1)))],
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IIC_SR>;
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} // Constraints = "$src = $dst"
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} // Constraints = "$src = $dst", SchedRW
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let SchedRW = [WriteShiftLd, WriteRMW] in {
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let Uses = [CL] in {
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def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
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"sar{b}\t{%cl, $dst|$dst, CL}",
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@ -330,13 +335,14 @@ def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
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"sar{q}\t$dst",
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[(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],
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IIC_SR>;
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} // SchedRW
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//===----------------------------------------------------------------------===//
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// Rotate instructions
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0 in {
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let Constraints = "$src1 = $dst" in {
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let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
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def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
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"rcl{b}\t$dst", [], IIC_SR>;
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def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
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@ -405,6 +411,7 @@ def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
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} // Constraints = "$src = $dst"
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let SchedRW = [WriteShiftLd, WriteRMW] in {
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def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
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"rcl{b}\t$dst", [], IIC_SR>;
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def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
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@ -458,9 +465,10 @@ def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
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def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
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"rcr{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
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}
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} // SchedRW
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} // hasSideEffects = 0
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let Constraints = "$src1 = $dst" in {
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let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
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// FIXME: provide shorter instructions when imm8 == 1
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let Uses = [CL] in {
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def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
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@ -512,8 +520,9 @@ def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
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"rol{q}\t$dst",
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[(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
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IIC_SR>;
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} // Constraints = "$src = $dst"
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} // Constraints = "$src = $dst", SchedRW
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let SchedRW = [WriteShiftLd, WriteRMW] in {
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let Uses = [CL] in {
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def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
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"rol{b}\t{%cl, $dst|$dst, CL}",
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@ -568,8 +577,9 @@ def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
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"rol{q}\t$dst",
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[(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
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IIC_SR>;
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} // SchedRW
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let Constraints = "$src1 = $dst" in {
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let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
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let Uses = [CL] in {
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def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
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"ror{b}\t{%cl, $dst|$dst, CL}",
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@ -620,8 +630,9 @@ def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
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"ror{q}\t$dst",
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[(set GR64:$dst, (rotr GR64:$src1, (i8 1)))],
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IIC_SR>;
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} // Constraints = "$src = $dst"
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} // Constraints = "$src = $dst", SchedRW
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let SchedRW = [WriteShiftLd, WriteRMW] in {
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let Uses = [CL] in {
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def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
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"ror{b}\t{%cl, $dst|$dst, CL}",
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@ -676,13 +687,14 @@ def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
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"ror{q}\t$dst",
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[(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
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IIC_SR>;
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} // SchedRW
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//===----------------------------------------------------------------------===//
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// Double shift instructions (generalizations of rotate)
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//===----------------------------------------------------------------------===//
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let Constraints = "$src1 = $dst" in {
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let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
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let Uses = [CL] in {
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def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
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@ -765,8 +777,9 @@ def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
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(i8 imm:$src3)))], IIC_SHD64_REG_IM>,
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TB;
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}
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} // Constraints = "$src = $dst"
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} // Constraints = "$src = $dst", SchedRW
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let SchedRW = [WriteShiftLd, WriteRMW] in {
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let Uses = [CL] in {
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def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
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"shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
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@ -840,6 +853,7 @@ def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
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(i8 imm:$src3)), addr:$dst)],
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IIC_SHD64_MEM_IM>,
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TB;
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} // SchedRW
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} // Defs = [EFLAGS]
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@ -857,12 +871,12 @@ multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> {
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let neverHasSideEffects = 1 in {
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def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i8imm:$src2),
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!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, TAXD, VEX;
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[]>, TAXD, VEX, Sched<[WriteShift]>;
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let mayLoad = 1 in
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def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst),
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(ins x86memop:$src1, i8imm:$src2),
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!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, TAXD, VEX;
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[]>, TAXD, VEX, Sched<[WriteShiftLd]>;
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}
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}
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@ -870,11 +884,17 @@ multiclass bmi_shift<string asm, RegisterClass RC, X86MemOperand x86memop> {
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let neverHasSideEffects = 1 in {
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def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
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!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
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VEX_4VOp3;
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VEX_4VOp3, Sched<[WriteShift]>;
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let mayLoad = 1 in
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def rm : I<0xF7, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
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!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
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VEX_4VOp3;
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VEX_4VOp3,
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Sched<[WriteShiftLd,
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// x86memop:$src1
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ReadDefault, ReadDefault, ReadDefault, ReadDefault,
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ReadDefault,
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// RC:$src1
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ReadAfterLd]>;
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}
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}
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