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[AMDGPU][MC] Corrected handling of tied src for atomic return MUBUF opcodes 

See bug 40917: https://bugs.llvm.org/show_bug.cgi?id=40917

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D59878

llvm-svn: 357249
This commit is contained in:
Dmitry Preobrazhensky 2019-03-29 12:16:04 +00:00
parent e074ac60b4
commit 7f33574be3
2 changed files with 15 additions and 7 deletions
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14
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
View File

@ -4911,13 +4911,19 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
bool HasLdsModifier = false;
OptionalImmIndexMap OptionalIdx;
assert(IsAtomicReturn ? IsAtomic : true);
unsigned FirstOperandIdx = 1;
for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
// Add the register arguments
if (Op.isReg()) {
Op.addRegOperands(Inst, 1);
// Insert a tied src for atomic return dst.
// This cannot be postponed as subsequent calls to
// addImmOperands rely on correct number of MC operands.
if (IsAtomicReturn && i == FirstOperandIdx)
Op.addRegOperands(Inst, 1);
continue;
}
@ -4955,12 +4961,6 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
}
}
// Copy $vdata_in operand and insert as $vdata for MUBUF_Atomic RTN insns.
if (IsAtomicReturn) {
MCInst::iterator I = Inst.begin(); // $vdata_in is always at the beginning.
Inst.insert(I, *I);
}
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);
if (!IsAtomic) { // glc is hard-coded.
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);

8
llvm/test/MC/AMDGPU/mubuf.s
View File

@ -711,6 +711,14 @@ buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc slc
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc slc ; encoding: [0x04,0x70,0xf0,0xe0,0x02,0x01,0x42,0xb8]
// VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc slc ; encoding: [0x04,0x70,0x2e,0xe1,0x02,0x01,0x02,0xb8]
buffer_atomic_add v5, off, s[8:11], 0.5 offset:4095 glc
// SICI: buffer_atomic_add v5, off, s[8:11], 0.5 offset:4095 glc ; encoding: [0xff,0x4f,0xc8,0xe0,0x00,0x05,0x02,0xf0]
// VI: buffer_atomic_add v5, off, s[8:11], 0.5 offset:4095 glc ; encoding: [0xff,0x4f,0x08,0xe1,0x00,0x05,0x02,0xf0]
buffer_atomic_add v5, off, s[8:11], 0.15915494 offset:4095 glc
// NOSICI: error: invalid operand for instruction
// VI: buffer_atomic_add v5, off, s[8:11], 0.15915494 offset:4095 glc ; encoding: [0xff,0x4f,0x08,0xe1,0x00,0x05,0x02,0xf8]
//===----------------------------------------------------------------------===//
// Lds support
//===----------------------------------------------------------------------===//