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[Hexagon] Adding combine reg-reg forms. 

llvm-svn: 223485
This commit is contained in:
Colin LeMahieu 2014-12-05 17:38:36 +00:00
parent b88ec656b5
commit 7f0a430c7d
2 changed files with 22 additions and 1 deletions
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15
llvm/lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -91,7 +91,7 @@ multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
}
//===----------------------------------------------------------------------===//
// ALU32/ALU (Instructions with register-register form)
// ALU32/ALU +
//===----------------------------------------------------------------------===//
def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
[SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
@ -155,6 +155,19 @@ class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
let Inst{4-0} = Rd;
}
class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp,
bit OpsRev>
: T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> {
let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")";
}
let isCodeGenOnly = 0 in {
def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>;
def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>;
def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>;
def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
}
multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
bit OpsRev> {
def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;

8
llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt
View File

@ -1,5 +1,13 @@
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
0x11 0xdf 0x95 0xf3
# CHECK: r17 = combine(r31.h, r21.h)
0x11 0xdf 0xb5 0xf3
# CHECK: r17 = combine(r31.h, r21.l)
0x11 0xdf 0xd5 0xf3
# CHECK: r17 = combine(r31.l, r21.h)
0x11 0xdf 0xf5 0xf3
# CHECK: r17 = combine(r31.l, r21.l)
0x11 0xc0 0x15 0x70
# CHECK: r17 = aslh(r21)
0x11 0xc0 0x35 0x70