parent
41334635cc
commit
7e859dd7f0
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@ -280,7 +280,14 @@ public:
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virtual bool addInstSelector(PassManagerBase &PM, bool Fast) {
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return true;
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}
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/// addPreRegAllocPasses - This method may be implemented by targets that want
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/// to run passes immediately before register allocation. This should return
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/// true if -print-machineinstrs should print after these passes.
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virtual bool addPreRegAlloc(PassManagerBase &PM, bool Fast) {
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return false;
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}
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/// addPostRegAllocPasses - This method may be implemented by targets that
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/// want to run passes after register allocation but before prolog-epilog
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/// insertion. This should return true if -print-machineinstrs should print
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@ -94,6 +94,10 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
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if (EnableSinking)
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PM.add(createMachineSinkingPass());
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// Run pre-ra passes.
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if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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// Perform register allocation to convert to a concrete x86 representation
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PM.add(createRegisterAllocator());
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