replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Recommit 'Remove the restriction that MachineSinking is now stopped by 

"insert_subreg, subreg_to_reg, and reg_sequence" instructions' after
adjusting some unittest checks.

This is to solve PR28852. The restriction was added at 2010 to make better register
coalescing. We assumed that it was not necessary any more. Testing results on x86
supported the assumption.

We will look closely to any performance impact it will bring and will be prepared
to help analyzing performance problem found on other architectures.

Differential Revision: https://reviews.llvm.org/D23210

llvm-svn: 278466
This commit is contained in:
Wei Mi 2016-08-12 03:33:22 +00:00
parent 2ab5f73d5a
commit 7e103d92cc
10 changed files with 348 additions and 308 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
llvm/include/llvm/Target/TargetInstrInfo.h
View File

@ -270,11 +270,8 @@ public:
/// MachineSink determines on its own whether the instruction is safe to sink;
/// this gives the target a hook to override the default behavior with regards
/// to which instructions should be sunk.
/// The default behavior is to not sink insert_subreg, subreg_to_reg, and
/// reg_sequence. These are meant to be close to the source to make it easier
/// to coalesce.
virtual bool shouldSink(const MachineInstr &MI) const {
return !MI.isInsertSubreg() && !MI.isSubregToReg() && !MI.isRegSequence();
return true;
}
/// Re-issue the specified 'original' instruction at the

7
llvm/test/CodeGen/AArch64/atomic-ops.ll
View File

@ -452,20 +452,19 @@ define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xchg_i32:
; CHECK: mov {{[xw]}}8, w[[OLD:[0-9]+]]
%old = atomicrmw xchg i32* @var32, i32 %offset release
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
; CHECK: .LBB{{[0-9]+}}_1:
; ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
; ; CHECK: ldxr {{[xw]}}[[OLD]], [x[[ADDR]]]
; w0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], w0, [x[[ADDR]]]
; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], w8, [x[[ADDR]]]
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
; CHECK-NOT: dmb
; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
ret i32 %old
}

4
llvm/test/CodeGen/ARM/2012-08-30-select.ll
View File

@ -2,8 +2,10 @@
; rdar://12201387
;CHECK-LABEL: select_s_v_v:
;CHECK: it ne
;CHECK: itee ne
;CHECK-NEXT: vmovne.i32
;CHECK-NEXT: vmoveq
;CHECK-NEXT: vmoveq
;CHECK: bx
define <16 x i8> @select_s_v_v(<16 x i8> %vec, i32 %avail) {
entry:

2
llvm/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 | grep mov | count 2
; RUN: llc < %s -march=x86-64 | grep mov | count 1
; rdar://6806252
define i64 @test(i32* %tmp13) nounwind {

37
llvm/test/CodeGen/X86/MachineSink-SubReg.ll Normal file
View File

@ -0,0 +1,37 @@
; PR28852: Check machine code sinking is not stopped by SUBREG_TO_REG.
; RUN: llc < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
; CHECK: foo
; CHECK-NOT: imull
; CHECK: retq
; CHECK: imull
define void @foo(i64 %value, i32 %kLengthBits, i32* nocapture %bits, i64* nocapture %bit_buffer_64, i32 %x) local_unnamed_addr {
entry:
%mul = mul i32 %x, %kLengthBits
%add = add i32 %mul, 3
%conv = zext i32 %add to i64
%mul2 = mul nuw nsw i64 %conv, 5
%sub = sub i64 64, %value
%conv4 = trunc i64 %sub to i32
%tmp0 = load i32, i32* %bits, align 4
%cmp = icmp ult i32 %tmp0, %conv4
br i1 %cmp, label %if.then, label %if.end, !prof !0
if.then: ; preds = %entry
%add7 = add i64 %mul2, %value
%tmp1 = load i64, i64* %bit_buffer_64, align 8
%add8 = add i64 %add7, %tmp1
store i64 %add8, i64* %bit_buffer_64, align 8
%conv9 = trunc i64 %mul2 to i32
store i32 %conv9, i32* %bits, align 4
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
!0 = !{!"branch_weights", i32 1, i32 2000}

18
llvm/test/CodeGen/X86/clz.ll
View File

@ -427,13 +427,14 @@ define i64 @ctlz_i64_zero_test(i64 %n) {
;
; X64-LABEL: ctlz_i64_zero_test:
; X64: # BB#0:
; X64-NEXT: movl $64, %eax
; X64-NEXT: testq %rdi, %rdi
; X64-NEXT: je .LBB11_2
; X64-NEXT: # BB#1: # %cond.false
; X64-NEXT: je .LBB11_1
; X64-NEXT: # BB#2: # %cond.false
; X64-NEXT: bsrq %rdi, %rax
; X64-NEXT: xorq $63, %rax
; X64-NEXT: .LBB11_2: # %cond.end
; X64-NEXT: retq
; X64-NEXT: .LBB11_1:
; X64-NEXT: movl $64, %eax
; X64-NEXT: retq
;
; X32-CLZ-LABEL: ctlz_i64_zero_test:
@ -601,12 +602,13 @@ define i64 @cttz_i64_zero_test(i64 %n) {
;
; X64-LABEL: cttz_i64_zero_test:
; X64: # BB#0:
; X64-NEXT: movl $64, %eax
; X64-NEXT: testq %rdi, %rdi
; X64-NEXT: je .LBB15_2
; X64-NEXT: # BB#1: # %cond.false
; X64-NEXT: je .LBB15_1
; X64-NEXT: # BB#2: # %cond.false
; X64-NEXT: bsfq %rdi, %rax
; X64-NEXT: .LBB15_2: # %cond.end
; X64-NEXT: retq
; X64-NEXT: .LBB15_1:
; X64-NEXT: movl $64, %eax
; X64-NEXT: retq
;
; X32-CLZ-LABEL: cttz_i64_zero_test:

8
llvm/test/CodeGen/X86/half.ll
View File

@ -157,8 +157,6 @@ define void @test_uitofp_i64(i64 %a, half* %p) #0 {
; CHECK-LABEL: test_uitofp_i64:
; CHECK-LIBCALL-NEXT: pushq [[ADDR:%[a-z0-9]+]]
; CHECK-LIBCALL-NEXT: movq %rsi, [[ADDR]]
; CHECK-NEXT: movl %edi, [[REG0:%[a-z0-9]+]]
; CHECK-NEXT: andl $1, [[REG0]]
; CHECK-NEXT: testq %rdi, %rdi
; CHECK-NEXT: js [[LABEL1:.LBB[0-9_]+]]
@ -169,8 +167,10 @@ define void @test_uitofp_i64(i64 %a, half* %p) #0 {
; convert using shift+or if negative
; CHECK-NEXT: [[LABEL1]]:
; CHECK-NEXT: shrq %rdi
; CHECK-NEXT: orq %rdi, [[REG2:%[a-z0-9]+]]
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: shrq %rax
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: orq %rax, [[REG2:%[a-z0-9]+]]
; CHECK-LIBCALL-NEXT: cvtsi2ssq [[REG2]], [[REG3:%[a-z0-9]+]]
; CHECK-LIBCALL-NEXT: addss [[REG3]], [[REG1]]
; CHECK-F16C-NEXT: vcvtsi2ssq [[REG2]], [[REG3:%[a-z0-9]+]], [[REG3]]

9
llvm/test/CodeGen/X86/machine-cse.ll
View File

@ -53,15 +53,15 @@ entry:
sw.bb: ; preds = %entry, %entry, %entry
; CHECK: %sw.bb
; CHECK: imull
; CHECK-NOT: imull
%mul = mul nsw i32 %test_case, 3
%mul20 = mul nsw i32 %mul, %scale
br i1 undef, label %if.end34, label %sw.bb307
if.end34: ; preds = %sw.bb
; CHECK: %if.end34
; CHECK: imull
; CHECK: leal
; CHECK-NOT: imull
tail call void (...) @printf(i32 %test_case, i32 %mul20) nounwind
%tmp = mul i32 %scale, %test_case
%tmp752 = mul i32 %tmp, 3
@ -104,12 +104,13 @@ return: ; preds = %if.end, %entry
; rdar://11393714
define i8* @bsd_memchr(i8* %s, i32 %a, i32 %c, i64 %n) nounwind ssp {
; CHECK: %entry
; CHECK: xorl
; CHECK-NOT: xorl
; CHECK: %preheader
; CHECK-NOT: xorl
; CHECK: %do.body
; CHECK-NOT: xorl
; CHECK: %do.cond
; CHECK-NOT: xorl
; CHECK: xorl
; CHECK: %return
entry:
%cmp = icmp eq i64 %n, 0

6
llvm/test/CodeGen/X86/uint64-to-float.ll
View File

@ -6,13 +6,15 @@
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin10.0.0"
; CHECK: andl
; CHECK: %entry
; CHECK-NEXT: testq %rdi, %rdi
; CHECK-NEXT: js LBB0_1
; CHECK: cvtsi2ss
; CHECK-NEXT: ret
; CHECK: LBB0_1
; CHECK: shrq
; CHECK: movq
; CHECK-NEXT: shrq
; CHECK-NEXT: andl
; CHECK-NEXT: orq
; CHECK-NEXT: cvtsi2ss
define float @test(i64 %a) {

560
llvm/test/CodeGen/X86/vec_int_to_fp.ll
View File

File diff suppressed because it is too large Load Diff