Hexagon - Add peephole optimizations for zero extends.
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a sequence of a pair of i32->i64 extensions followed by a "bitwise or" into COMBINE_rr. * lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg. * test/CodeGen/Hexagon/union-1.ll: New test. * test/CodeGen/Hexagon/combine_ir.ll: Fix test. llvm-svn: 180946
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@ -2529,6 +2529,27 @@ def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
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(i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
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let AddedComplexity = 100 in
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def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
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(i32 32))),
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(i64 (zextloadi32 (i32 (add IntRegs:$src2,
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s11_2ExtPred:$offset2)))))),
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(i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
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(LDriw_indexed IntRegs:$src2,
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s11_2ExtPred:$offset2)))>;
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def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
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(i32 32))),
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(i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
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(i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
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(LDriw ADDRriS11_2:$srcLow)))>;
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def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
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(i32 32))),
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(i64 (zext (i32 IntRegs:$srcLow))))),
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(i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
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IntRegs:$srcLow))>;
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let AddedComplexity = 100 in
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def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
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(i32 32))),
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@ -73,6 +73,10 @@ static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Optimization of Sign/Zero Extends"));
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static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Optimization of extensions to i64."));
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namespace {
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struct HexagonPeephole : public MachineFunctionPass {
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const HexagonInstrInfo *QII;
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@ -142,6 +146,21 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
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}
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}
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// Look for %vreg170<def> = COMBINE_ir_V4 (0, %vreg169)
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// %vreg170:DoublRegs, %vreg169:IntRegs
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if (!DisableOptExtTo64 &&
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MI->getOpcode () == Hexagon::COMBINE_Ir_V4) {
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assert (MI->getNumOperands() == 3);
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MachineOperand &Dst = MI->getOperand(0);
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MachineOperand &Src1 = MI->getOperand(1);
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MachineOperand &Src2 = MI->getOperand(2);
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if (Src1.getImm() != 0)
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continue;
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unsigned DstReg = Dst.getReg();
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unsigned SrcReg = Src2.getReg();
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PeepholeMap[DstReg] = SrcReg;
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}
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// Look for this sequence below
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// %vregDoubleReg1 = LSRd_ri %vregDoubleReg0, 32
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// %vregIntReg = COPY %vregDoubleReg1:subreg_loreg.
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@ -6,12 +6,7 @@ define void @word(i32* nocapture %a) nounwind {
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entry:
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%0 = load i32* %a, align 4, !tbaa !0
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%1 = zext i32 %0 to i64
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%add.ptr = getelementptr inbounds i32* %a, i32 1
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%2 = load i32* %add.ptr, align 4, !tbaa !0
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%3 = zext i32 %2 to i64
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%4 = shl nuw i64 %3, 32
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%ins = or i64 %4, %1
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tail call void @bar(i64 %ins) nounwind
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tail call void @bar(i64 %1) nounwind
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ret void
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}
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@ -0,0 +1,23 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; CHECK: word
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; CHECK-NOT: combine(#0
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; CHECK: jump bar
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define void @word(i32* nocapture %a) nounwind {
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entry:
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%0 = load i32* %a, align 4, !tbaa !0
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%1 = zext i32 %0 to i64
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%add.ptr = getelementptr inbounds i32* %a, i32 1
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%2 = load i32* %add.ptr, align 4, !tbaa !0
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%3 = zext i32 %2 to i64
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%4 = shl nuw i64 %3, 32
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%ins = or i64 %4, %1
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tail call void @bar(i64 %ins) nounwind
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ret void
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}
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declare void @bar(i64)
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!0 = metadata !{metadata !"int", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA"}
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