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RegisterScavenger: Take a reference as enterBasicBlock() argument. 

Make it obvious that the argument cannot be nullptr.
Remove an unnecessary nullptr check in initRegState.

llvm-svn: 265511
This commit is contained in:
Matthias Braun 2016-04-06 02:47:09 +00:00
parent 61da4cef6c
commit 7dc03f060e
10 changed files with 16 additions and 19 deletions
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4
llvm/include/llvm/CodeGen/RegisterScavenging.h
View File

@ -71,8 +71,8 @@ public:
RegScavenger()
: MBB(nullptr), NumRegUnits(0), Tracking(false) {}
/// Start tracking liveness from the begin of the specific basic block.
void enterBasicBlock(MachineBasicBlock *mbb);
/// Start tracking liveness from the begin of basic block \p MBB.
void enterBasicBlock(MachineBasicBlock &MBB);
/// Move the internal MBB iterator and update register states.
void forward();

2
llvm/lib/CodeGen/BranchFolding.cpp
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@ -397,7 +397,7 @@ static unsigned ComputeCommonTailLength(MachineBasicBlock *MBB1,
void BranchFolder::MaintainLiveIns(MachineBasicBlock *CurMBB,
MachineBasicBlock *NewMBB) {
if (RS) {
RS->enterBasicBlock(CurMBB);
RS->enterBasicBlock(*CurMBB);
if (!CurMBB->empty())
RS->forward(std::prev(CurMBB->end()));
for (unsigned int i = 1, e = TRI->getNumRegs(); i != e; i++)

4
llvm/lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -880,7 +880,7 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn,
unsigned FrameSetupOpcode = TII.getCallFrameSetupOpcode();
unsigned FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
if (RS && !FrameIndexVirtualScavenging) RS->enterBasicBlock(BB);
if (RS && !FrameIndexVirtualScavenging) RS->enterBasicBlock(*BB);
bool InsideCallSequence = false;
@ -991,7 +991,7 @@ PEI::scavengeFrameVirtualRegs(MachineFunction &Fn) {
// Run through the instructions and find any virtual registers.
for (MachineFunction::iterator BB = Fn.begin(),
E = Fn.end(); BB != E; ++BB) {
RS->enterBasicBlock(&*BB);
RS->enterBasicBlock(*BB);
int SPAdj = 0;

11
llvm/lib/CodeGen/RegisterScavenging.cpp
View File

@ -49,9 +49,6 @@ void RegScavenger::initRegState() {
// All register units start out unused.
RegUnitsAvailable.set();
if (!MBB)
return;
// Live-in registers are in use.
for (const auto &LI : MBB->liveins())
setRegUsed(LI.PhysReg, LI.LaneMask);
@ -63,8 +60,8 @@ void RegScavenger::initRegState() {
setRegUsed(I);
}
void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
MachineFunction &MF = *mbb->getParent();
void RegScavenger::enterBasicBlock(MachineBasicBlock &MBB) {
MachineFunction &MF = *MBB.getParent();
TII = MF.getSubtarget().getInstrInfo();
TRI = MF.getSubtarget().getRegisterInfo();
MRI = &MF.getRegInfo();
@ -78,15 +75,15 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
"Cannot use register scavenger with inaccurate liveness");
// Self-initialize.
if (!MBB) {
if (!this->MBB) {
NumRegUnits = TRI->getNumRegUnits();
RegUnitsAvailable.resize(NumRegUnits);
KillRegUnits.resize(NumRegUnits);
DefRegUnits.resize(NumRegUnits);
TmpRegUnits.resize(NumRegUnits);
}
this->MBB = &MBB;
MBB = mbb;
initRegState();
Tracking = false;

2
llvm/lib/CodeGen/TailDuplication.cpp
View File

@ -816,7 +816,7 @@ TailDuplicatePass::TailDuplicate(MachineBasicBlock *TailBB,
if (RS && !TailBB->livein_empty()) {
// Update PredBB livein.
RS->enterBasicBlock(PredBB);
RS->enterBasicBlock(*PredBB);
if (!PredBB->empty())
RS->forward(std::prev(PredBB->end()));
for (const auto &LI : TailBB->liveins()) {

2
llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
View File

@ -497,7 +497,7 @@ bool AArch64A57FPLoadBalancing::colorChainSet(std::vector<Chain*> GV,
int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C,
MachineBasicBlock &MBB) {
RegScavenger RS;
RS.enterBasicBlock(&MBB);
RS.enterBasicBlock(MBB);
RS.forward(MachineBasicBlock::iterator(G->getStart()));
// Can we find an appropriate register that is available throughout the life

2
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -744,7 +744,7 @@ unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
Entry.addLiveIn(Reg);
}
RS->enterBasicBlock(&Entry);
RS->enterBasicBlock(Entry);
// FIXME: Can we scavenge an SReg_64 and access the subregs?
unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);

2
llvm/lib/Target/Mips/Mips16InstrInfo.cpp
View File

@ -326,7 +326,7 @@ unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
int Reg =0;
int SpReg = 0;
rs.enterBasicBlock(&MBB);
rs.enterBasicBlock(MBB);
rs.forward(II);
//
// We need to know which registers can be used, in the case where there

2
llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
View File

@ -596,7 +596,7 @@ PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB,
(!UseAtEnd && (&MBB->getParent()->front() == MBB)))
return true;
RS.enterBasicBlock(MBB);
RS.enterBasicBlock(*MBB);
if (UseAtEnd && !MBB->empty()) {
// The scratch register will be used at the end of the block, so must

4
llvm/lib/Target/WebAssembly/WebAssemblyPEI.cpp
View File

@ -867,7 +867,7 @@ void WasmPEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn,
unsigned FrameSetupOpcode = TII.getCallFrameSetupOpcode();
unsigned FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
if (RS && !FrameIndexVirtualScavenging) RS->enterBasicBlock(BB);
if (RS && !FrameIndexVirtualScavenging) RS->enterBasicBlock(*BB);
bool InsideCallSequence = false;
@ -977,7 +977,7 @@ WasmPEI::scavengeFrameVirtualRegs(MachineFunction &Fn) {
// Run through the instructions and find any virtual registers.
for (MachineFunction::iterator BB = Fn.begin(),
E = Fn.end(); BB != E; ++BB) {
RS->enterBasicBlock(&*BB);
RS->enterBasicBlock(*BB);
int SPAdj = 0;