Adding skeleton for unit testing Hexagon Code Emission
Adding and modifying CMakeLists.txt files to run unit tests under unittests/Target/* if the directory exists. Adding basic unit test to check that code emitter object can be retrieved. Differential Revision: http://reviews.llvm.org/D5523 Change by: Colin LeMahieu llvm-svn: 218986
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@ -2,6 +2,7 @@ set(LLVM_TARGET_DEFINITIONS Hexagon.td)
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tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
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tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
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@ -1,5 +1,8 @@
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add_llvm_library(LLVMHexagonDesc
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add_llvm_library(LLVMHexagonDesc
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HexagonMCAsmInfo.cpp
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HexagonMCAsmInfo.cpp
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HexagonMCCodeEmitter.cpp
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HexagonMCInst.cpp
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HexagonMCInst.cpp
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HexagonMCTargetDesc.cpp
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HexagonMCTargetDesc.cpp
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)
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)
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add_dependencies(LLVMHexagonDesc HexagonCommonTableGen)
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@ -0,0 +1,88 @@
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//===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonMCCodeEmitter.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "MCTargetDesc/HexagonMCInst.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "mccodeemitter"
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using namespace llvm;
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using namespace Hexagon;
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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namespace {
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/// \brief 10.6 Instruction Packets
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/// \brief Possible values for instruction packet parse field.
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enum class ParseField { duplex = 0x0, last0 = 0x1, last1 = 0x2, end = 0x3 };
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/// \brief Returns the packet bits based on instruction position.
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uint32_t getPacketBits(HexagonMCInst const &HMI) {
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unsigned const ParseFieldOffset = 14;
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ParseField Field = HMI.isPacketEnd() ? ParseField::end : ParseField::last0;
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return static_cast <uint32_t> (Field) << ParseFieldOffset;
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}
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void emitLittleEndian(uint64_t Binary, raw_ostream &OS) {
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OS << static_cast<uint8_t>((Binary >> 0x00) & 0xff);
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OS << static_cast<uint8_t>((Binary >> 0x08) & 0xff);
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OS << static_cast<uint8_t>((Binary >> 0x10) & 0xff);
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OS << static_cast<uint8_t>((Binary >> 0x18) & 0xff);
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}
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}
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HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
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MCSubtargetInfo const &aMST,
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MCContext &aMCT)
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: MST(aMST), MCT(aMCT) {}
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void HexagonMCCodeEmitter::EncodeInstruction(MCInst const &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const {
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HexagonMCInst const &HMB = static_cast<HexagonMCInst const &>(MI);
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uint64_t Binary = getBinaryCodeForInstr(HMB, Fixups, STI) | getPacketBits(HMB);
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assert(HMB.getDesc().getSize() == 4 && "All instructions should be 32bit");
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emitLittleEndian(Binary, OS);
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++MCNumEmitted;
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}
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unsigned
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HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const {
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if (MO.isReg())
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return MCT.getRegisterInfo()->getEncodingValue(MO.getReg());
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if (MO.isImm())
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return static_cast<unsigned>(MO.getImm());
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llvm_unreachable("Only Immediates and Registers implemented right now");
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}
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MCSubtargetInfo const &HexagonMCCodeEmitter::getSubtargetInfo() const {
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return MST;
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}
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MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
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MCRegisterInfo const &MRI,
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MCSubtargetInfo const &MST,
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MCContext &MCT) {
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return new HexagonMCCodeEmitter(MII, MST, MCT);
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}
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#include "HexagonGenMCCodeEmitter.inc"
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@ -0,0 +1,60 @@
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//===-- HexagonMCCodeEmitter.h - Hexagon Target Descriptions ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief Definition for classes that emit Hexagon machine code from MCInsts
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///
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//===----------------------------------------------------------------------===//
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#ifndef HEXAGONMCCODEEMITTER_H
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#define HEXAGONMCCODEEMITTER_H
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/raw_ostream.h"
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namespace llvm {
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class HexagonMCCodeEmitter : public MCCodeEmitter {
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MCSubtargetInfo const &MST;
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MCContext &MCT;
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public:
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HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCSubtargetInfo const &aMST,
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MCContext &aMCT);
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MCSubtargetInfo const &getSubtargetInfo() const;
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void EncodeInstruction(MCInst const &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const override;
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// getBinaryCodeForInstr - TableGen'erated function for getting the
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// binary encoding for an instruction.
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uint64_t getBinaryCodeForInstr(MCInst const &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const;
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/// \brief Return binary encoding of operand.
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unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const;
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private:
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HexagonMCCodeEmitter(HexagonMCCodeEmitter const &) = delete;
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void operator=(HexagonMCCodeEmitter const &) = delete;
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}; // class HexagonMCCodeEmitter
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} // namespace llvm
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#endif /* HEXAGONMCCODEEMITTER_H */
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@ -46,9 +46,8 @@ static MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT) {
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return X;
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return X;
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}
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}
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static MCSubtargetInfo *createHexagonMCSubtargetInfo(StringRef TT,
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static MCSubtargetInfo *
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StringRef CPU,
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createHexagonMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) {
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StringRef FS) {
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MCSubtargetInfo *X = new MCSubtargetInfo();
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MCSubtargetInfo *X = new MCSubtargetInfo();
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InitHexagonMCSubtargetInfo(X, TT, CPU, FS);
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InitHexagonMCSubtargetInfo(X, TT, CPU, FS);
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return X;
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return X;
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MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
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MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
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// VirtualFP = (R30 + #0).
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// VirtualFP = (R30 + #0).
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MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
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MCCFIInstruction Inst =
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nullptr, Hexagon::R30, 0);
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MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0);
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MAI->addInitialFrameState(Inst);
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MAI->addInitialFrameState(Inst);
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return MAI;
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return MAI;
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@ -86,7 +85,8 @@ extern "C" void LLVMInitializeHexagonTargetMC() {
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createHexagonMCCodeGenInfo);
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createHexagonMCCodeGenInfo);
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// Register the MC instruction info.
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget, createHexagonMCInstrInfo);
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TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget,
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createHexagonMCInstrInfo);
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// Register the MC register info.
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(TheHexagonTarget,
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TargetRegistry::RegisterMCRegInfo(TheHexagonTarget,
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// Register the MC subtarget info.
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(TheHexagonTarget,
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TargetRegistry::RegisterMCSubtargetInfo(TheHexagonTarget,
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createHexagonMCSubtargetInfo);
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createHexagonMCSubtargetInfo);
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// Register the MC Code Emitter
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TargetRegistry::RegisterMCCodeEmitter(TheHexagonTarget,
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createHexagonMCCodeEmitter);
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}
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}
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#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
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#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
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namespace llvm {
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namespace llvm {
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class MCSubtargetInfo;
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class Target;
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class Target;
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extern Target TheHexagonTarget;
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extern Target TheHexagonTarget;
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MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &MST,
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MCContext &MCT);
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} // End llvm namespace
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} // End llvm namespace
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// Define symbolic names for Hexagon registers. This defines a mapping from
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// Define symbolic names for Hexagon registers. This defines a mapping from
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@ -7,3 +7,9 @@ add_llvm_unittest(MCTests
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StringTableBuilderTest.cpp
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StringTableBuilderTest.cpp
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YAMLTest.cpp
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YAMLTest.cpp
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)
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)
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foreach(t ${LLVM_TARGETS_TO_BUILD})
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if (IS_DIRECTORY "${CMAKE_CURRENT_LIST_DIR}/${t}")
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add_subdirectory(${t})
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endif (IS_DIRECTORY "${CMAKE_CURRENT_LIST_DIR}/${t}")
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endforeach()
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