From 7cea91e1719fbf054821927b3ed7158b42929d75 Mon Sep 17 00:00:00 2001
From: Anton Korobeynikov <asl@math.spbu.ru>
Date: Wed, 21 Oct 2009 00:11:44 +0000
Subject: [PATCH] Add reg-imm tests

llvm-svn: 84705
---
 llvm/test/CodeGen/MSP430/Inst16ri.ll | 37 ++++++++++++++++++++++++++++
 llvm/test/CodeGen/MSP430/Inst8ri.ll  | 37 ++++++++++++++++++++++++++++
 2 files changed, 74 insertions(+)
 create mode 100644 llvm/test/CodeGen/MSP430/Inst16ri.ll
 create mode 100644 llvm/test/CodeGen/MSP430/Inst8ri.ll

diff --git a/llvm/test/CodeGen/MSP430/Inst16ri.ll b/llvm/test/CodeGen/MSP430/Inst16ri.ll
new file mode 100644
index 000000000000..5115a236929c
--- /dev/null
+++ b/llvm/test/CodeGen/MSP430/Inst16ri.ll
@@ -0,0 +1,37 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+
+define i16 @mov() nounwind {
+; CHECK: mov:
+; CHECK: mov.w	#1, r15
+	ret i16 1
+}
+
+define i16 @add(i16 %a, i16 %b) nounwind {
+; CHECK: add:
+; CHECK: add.w	#1, r15
+	%1 = add i16 %a, 1
+	ret i16 %1
+}
+
+define i16 @and(i16 %a, i16 %b) nounwind {
+; CHECK: and:
+; CHECK: and.w	#1, r15
+	%1 = and i16 %a, 1
+	ret i16 %1
+}
+
+define i16 @bis(i16 %a, i16 %b) nounwind {
+; CHECK: bis:
+; CHECK: bis.w	#1, r15
+	%1 = or i16 %a, 1
+	ret i16 %1
+}
+
+define i16 @xor(i16 %a, i16 %b) nounwind {
+; CHECK: xor:
+; CHECK: xor.w	#1, r15
+	%1 = xor i16 %a, 1
+	ret i16 %1
+}
diff --git a/llvm/test/CodeGen/MSP430/Inst8ri.ll b/llvm/test/CodeGen/MSP430/Inst8ri.ll
new file mode 100644
index 000000000000..ac3418aa6c7b
--- /dev/null
+++ b/llvm/test/CodeGen/MSP430/Inst8ri.ll
@@ -0,0 +1,37 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+
+define i8 @mov() nounwind {
+; CHECK: mov:
+; CHECK: mov.b	#1, r15
+	ret i8 1
+}
+
+define i8 @add(i8 %a, i8 %b) nounwind {
+; CHECK: add:
+; CHECK: add.b	#1, r15
+	%1 = add i8 %a, 1
+	ret i8 %1
+}
+
+define i8 @and(i8 %a, i8 %b) nounwind {
+; CHECK: and:
+; CHECK: and.b	#1, r15
+	%1 = and i8 %a, 1
+	ret i8 %1
+}
+
+define i8 @bis(i8 %a, i8 %b) nounwind {
+; CHECK: bis:
+; CHECK: bis.b	#1, r15
+	%1 = or i8 %a, 1
+	ret i8 %1
+}
+
+define i8 @xor(i8 %a, i8 %b) nounwind {
+; CHECK: xor:
+; CHECK: xor.b	#1, r15
+	%1 = xor i8 %a, 1
+	ret i8 %1
+}