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evert "[mips] Fix test mips64fpldst.ll with machine verifier enabled" 

This reverts commit r301394. It broke some internal buildbots, reverting
while the issue is being investigated.

llvm-svn: 304896
This commit is contained in:
Simon Dardis 2017-06-07 11:21:37 +00:00
parent 0641b8b4d3
commit 7c96ba1920
9 changed files with 46 additions and 20 deletions
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6
llvm/lib/Target/Mips/MipsMachineFunction.cpp
View File

@ -40,7 +40,11 @@ unsigned MipsFunctionInfo::getGlobalBaseReg() {
const TargetRegisterClass *RC =
STI.inMips16Mode()
? &Mips::CPU16RegsRegClass
: static_cast<const MipsTargetMachine &>(MF.getTarget())
: STI.inMicroMipsMode()
? STI.hasMips64()
? &Mips::GPRMM16_64RegClass
: &Mips::GPRMM16RegClass
: static_cast<const MipsTargetMachine &>(MF.getTarget())
.getABI()
.IsN64()
? &Mips::GPR64RegClass

2
llvm/test/CodeGen/Mips/llvm-ir/mul.ll
View File

@ -268,7 +268,7 @@ entry:
; MM64R6: daddu $2, $[[T1]], $[[T0]]
; MM64R6-DAG: dmul $3, $5, $7
; MM32: lw $25, %call16(__multi3)($gp)
; MM32: lw $25, %call16(__multi3)($16)
%r = mul i128 %a, %b
ret i128 %r

12
llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
View File

@ -172,7 +172,7 @@ entry:
; 64R6: ddiv $2, $4, $5
; 64R6: teq $5, $zero, 7
; MM32: lw $25, %call16(__divdi3)($gp)
; MM32: lw $25, %call16(__divdi3)($2)
; MM64: ddiv $2, $4, $5
; MM64: teq $5, $zero, 7
@ -184,7 +184,15 @@ entry:
define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) {
entry:
; ALL-LABEL: sdiv_i128:
; ALL: l{{w|d}} $25, %call16(__divti3)($gp)
; GP32: lw $25, %call16(__divti3)($gp)
; GP64-NOT-R6: ld $25, %call16(__divti3)($gp)
; 64R6: ld $25, %call16(__divti3)($gp)
; MM32: lw $25, %call16(__divti3)($16)
; MM64: ld $25, %call16(__divti3)($2)
%r = sdiv i128 %a, %b
ret i128 %r

11
llvm/test/CodeGen/Mips/llvm-ir/srem.ll
View File

@ -164,7 +164,7 @@ entry:
; 64R6: dmod $2, $4, $5
; 64R6: teq $5, $zero, 7
; MM32: lw $25, %call16(__moddi3)($gp)
; MM32: lw $25, %call16(__moddi3)($2)
; MM64: dmod $2, $4, $5
; MM64: teq $5, $zero, 7
@ -177,7 +177,14 @@ define signext i128 @srem_i128(i128 signext %a, i128 signext %b) {
entry:
; ALL-LABEL: srem_i128:
; ALL: l{{w|d}} $25, %call16(__modti3)($gp)
; GP32: lw $25, %call16(__modti3)($gp)
; GP64-NOT-R6: ld $25, %call16(__modti3)($gp)
; 64R6: ld $25, %call16(__modti3)($gp)
; MM32: lw $25, %call16(__modti3)($16)
; MM64: ld $25, %call16(__modti3)($2)
%r = srem i128 %a, %b
ret i128 %r

11
llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
View File

@ -134,7 +134,7 @@ entry:
; 64R6: ddivu $2, $4, $5
; 64R6: teq $5, $zero, 7
; MM32: lw $25, %call16(__udivdi3)($gp)
; MM32: lw $25, %call16(__udivdi3)($2)
; MM64: ddivu $2, $4, $5
; MM64: teq $5, $zero, 7
@ -147,7 +147,14 @@ define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) {
entry:
; ALL-LABEL: udiv_i128:
; ALL: l{{w|d}} $25, %call16(__udivti3)($gp)
; GP32: lw $25, %call16(__udivti3)($gp)
; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp)
; 64-R6: ld $25, %call16(__udivti3)($gp)
; MM32: lw $25, %call16(__udivti3)($16)
; MM64: ld $25, %call16(__udivti3)($2)
%r = udiv i128 %a, %b
ret i128 %r

6
llvm/test/CodeGen/Mips/llvm-ir/urem.ll
View File

@ -190,7 +190,7 @@ entry:
; 64R6: dmodu $2, $4, $5
; 64R6: teq $5, $zero, 7
; MM32: lw $25, %call16(__umoddi3)($gp)
; MM32: lw $25, %call16(__umoddi3)($2)
; MM64: dmodu $2, $4, $5
; MM64: teq $5, $zero, 7
@ -208,9 +208,9 @@ entry:
; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp)
; 64R6: ld $25, %call16(__umodti3)($gp)
; MM32: lw $25, %call16(__umodti3)($gp)
; MM32: lw $25, %call16(__umodti3)($16)
; MM64: ld $25, %call16(__umodti3)($gp)
; MM64: ld $25, %call16(__umodti3)($2)
%r = urem i128 %a, %b
ret i128 %r

2
llvm/test/CodeGen/Mips/micromips-gp-rc.ll
View File

@ -14,5 +14,5 @@ entry:
; Function Attrs: noreturn
declare void @exit(i32 signext)
; CHECK: addu $gp, ${{[0-9]+}}
; CHECK: move $gp, ${{[0-9]+}}

12
llvm/test/CodeGen/Mips/mips64fpldst.ll
View File

@ -1,9 +1,9 @@
; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N64
; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N32
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N64
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N32
; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N32
; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N64
; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
@f0 = common global float 0.000000e+00, align 4
@d0 = common global double 0.000000e+00, align 8

4
llvm/test/CodeGen/Mips/tailcall/tailcall.ll
View File

@ -176,7 +176,7 @@ entry:
; ALL-LABEL: caller8_1:
; PIC32: jalr $25
; PIC32R6: jalr $25
; PIC32MM: jalr{{.*}} $25
; PIC32MM: jalr $25
; STATIC32: jal
; PIC64: jalr $25
; STATIC64: jal
@ -288,7 +288,7 @@ entry:
; ALL-LABEL: caller13:
; PIC32: jalr $25
; PIC32R6: jalr $25
; PIC32MM: jalr{{.*}} $25
; PIC32MM: jalr $25
; STATIC32: jal
; STATIC64: jal
; PIC64R6: jalr $25