parent
19e44b4510
commit
7c699f92cd
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@ -95,7 +95,7 @@ bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
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!SrcSubIdx && !DstSubIdx) {
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const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
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const TargetRegisterClass *RC = MRI->getRegClass(Reg);
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if (SRC == RC || SRC->hasSubClass(RC) || RC->hasSubClass(SRC)) {
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if (SRC == RC || RC->hasSubClass(SRC)) {
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DEBUG(dbgs() << "Coalescing: " << *DefMI);
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DEBUG(dbgs() << "*** to: " << *MI);
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MO.setReg(SrcReg);
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