AMDGPU/GlobalISel: Add support for G_INTTOPTR
Summary: This is a no-op. Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D52916 llvm-svn: 343839
This commit is contained in:
Tom Stellard
parent
d2a293c562
commit
7c65078f04
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@ -630,6 +630,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I,
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return selectImpl(I, CoverageInfo);
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case TargetOpcode::G_ADD:
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return selectG_ADD(I);
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case TargetOpcode::G_INTTOPTR:
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case TargetOpcode::G_BITCAST:
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return selectCOPY(I);
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case TargetOpcode::G_CONSTANT:
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@ -117,6 +117,10 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
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setAction({G_ICMP, S1}, Legal);
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setAction({G_ICMP, 1, S32}, Legal);
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getActionDefinitionsBuilder(G_INTTOPTR)
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.legalIf([](const LegalityQuery &Query) {
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return true;
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});
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getActionDefinitionsBuilder({G_LOAD, G_STORE})
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.legalIf([=, &ST](const LegalityQuery &Query) {
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@ -402,6 +402,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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OpdsMapping[i] = AMDGPU::getValueMapping(Bank, SrcSize);
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break;
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}
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case AMDGPU::G_INTTOPTR:
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case AMDGPU::G_BITCAST: {
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unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
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@ -0,0 +1,34 @@
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# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
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--- |
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define amdgpu_kernel void @inttoptr(i32 addrspace(4)* %const0, i32 addrspace(0)* %flat0) {ret void}
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...
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---
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name: inttoptr
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legalized: true
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regBankSelected: true
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# GCN-LABEL: name: inttoptr
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# GCN: [[S64:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
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# GCN: [[V64:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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# FIXME: This extra copy is unnecessary, but is it the instruction selector's
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# job to clean this up?
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# GCN: [[S64_COPY:%[0-9]+]]:sreg_64 = COPY [[S64]]
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# GCN: [[VAL:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[S64_COPY]], 0, 0
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# GCN: [[V_VAL:%[0-9]+]]:vgpr_32 = COPY [[VAL]]
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# GCN: FLAT_STORE_DWORD [[V64]], [[V_VAL]]
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#
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:vgpr(s64) = COPY $vgpr0_vgpr1
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%2:sgpr(p4) = G_INTTOPTR %0
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%3:sgpr(s32) = G_LOAD %2 :: (load 4 from %ir.const0)
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%4:vgpr(p0) = G_INTTOPTR %1
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%5:vgpr(s32) = COPY %3
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G_STORE %5, %4 :: (store 4 into %ir.flat0)
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...
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---
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@ -0,0 +1,29 @@
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# RUN: llc -march=amdgcn -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: test_inttoptr
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2, $vgpr0_vgpr1, $vgpr2
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; CHECK-LABEL: name: test_inttoptr
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; CHECK: [[S64:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
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; CHECK: [[S32:%[0-9]+]]:_(s32) = COPY $sgpr2
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; CHECK: [[V64:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[V32:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: (p0) = G_INTTOPTR [[V64]]
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; CHECK: (p1) = G_INTTOPTR [[V64]]
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; CHECK: (p3) = G_INTTOPTR [[V32]]
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; CHECK: (p4) = G_INTTOPTR [[S64]]
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; CHECK: (p5) = G_INTTOPTR [[S32]]
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%0:_(s64) = COPY $sgpr0_sgpr1
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%1:_(s32) = COPY $sgpr2
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%2:_(s64) = COPY $vgpr0_vgpr1
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%3:_(s32) = COPY $vgpr2
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%4:_(p0) = G_INTTOPTR %2
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%5:_(p1) = G_INTTOPTR %2
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%6:_(p3) = G_INTTOPTR %3
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%7:_(p4) = G_INTTOPTR %0
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%8:_(p5) = G_INTTOPTR %1
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S_ENDPGM implicit %4, implicit %5, implicit %6, implicit %7, implicit %8
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...
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@ -0,0 +1,31 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
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# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
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---
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name: inttoptr_s
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: inttoptr_s
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
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; CHECK: [[INTTOPTR:%[0-9]+]]:sgpr(p4) = G_INTTOPTR [[COPY]](s64)
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%0:_(s64) = COPY $sgpr0_sgpr1
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%1:_(p4) = G_INTTOPTR %0
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...
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---
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name: inttoptr_v
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: inttoptr_v
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[INTTOPTR:%[0-9]+]]:vgpr(p0) = G_INTTOPTR [[COPY]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(p0) = G_INTTOPTR %0
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...
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