replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Renaming variables to coincide with documentation. No functionality change. 

llvm-svn: 120522
This commit is contained in:
Bill Wendling 2010-12-01 01:32:02 +00:00
parent 83b0918938
commit 7c646b924b
2 changed files with 21 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Target/ARM/ARMInstrFormats.td
View File

@ -861,7 +861,7 @@ class T1pI<dag oops, dag iops, InstrItinClass itin,
class T1pIt<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
"$lhs = $dst", pattern>;
"$Rn = $Rdn", pattern>;
class T1pIs<dag oops, dag iops,
InstrItinClass itin, string opc, string asm, list<dag> pattern>

40
llvm/lib/Target/ARM/ARMInstrThumb.td
View File

@ -790,15 +790,15 @@ def tADDrr : // A8.6.6 T1
[(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
let neverHasSideEffects = 1 in
def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
"add", "\t$dst, $rhs", []>,
def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
"add", "\t$Rdn, $Rm", []>,
T1Special<{0,0,?,?}> {
// A8.6.6 T2
bits<4> dst;
bits<4> rhs;
let Inst{6-3} = rhs;
let Inst{7} = dst{3};
let Inst{2-0} = dst{2-0};
bits<4> Rdn;
bits<4> Rm;
let Inst{7} = Rdn{3};
let Inst{6-3} = Rm;
let Inst{2-0} = Rdn{2-0};
}
// AND register
@ -1192,24 +1192,24 @@ let usesCustomInserter = 1 in // Expanded after instruction selection.
// 16-bit movcc in IT blocks for Thumb2.
let neverHasSideEffects = 1 in {
def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
"mov", "\t$dst, $rhs", []>,
def tMOVCCr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iCMOVr,
"mov", "\t$Rdn, $Rm", []>,
T1Special<{1,0,?,?}> {
bits<4> rhs;
bits<4> dst;
let Inst{7} = dst{3};
let Inst{6-3} = rhs;
let Inst{2-0} = dst{2-0};
bits<4> Rdn;
bits<4> Rm;
let Inst{7} = Rdn{3};
let Inst{6-3} = Rm;
let Inst{2-0} = Rdn{2-0};
}
let isMoveImm = 1 in
def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
"mov", "\t$dst, $rhs", []>,
def tMOVCCi : T1pIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$Rm), IIC_iCMOVi,
"mov", "\t$Rdn, $Rm", []>,
T1General<{1,0,0,?,?}> {
bits<8> rhs;
bits<3> dst;
let Inst{10-8} = dst;
let Inst{7-0} = rhs;
bits<3> Rdn;
bits<8> Rm;
let Inst{10-8} = Rdn;
let Inst{7-0} = Rm;
}
} // neverHasSideEffects