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[PowerPC] Enable printing instructions using aliases 

TableGen had been nicely generating code to print a number of instructions using
shorter aliases (and PowerPC has plenty of short mnemonics), but we were not
calling it. For some of the aliases we support in the parser, TableGen can't
infer the "inverse" alias relationship, so there is still more to do.

Thus, after some hours of updating test cases...

llvm-svn: 235616
This commit is contained in:
Hal Finkel 2015-04-23 18:30:38 +00:00
parent 9cf4f2c2d8
commit 7c5cb066d0
55 changed files with 1273 additions and 1280 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
View File

@ -31,6 +31,7 @@ static cl::opt<bool>
FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
cl::desc("Use full register names when printing assembly"));
#define PRINT_ALIAS_INSTR
#include "PPCGenAsmWriter.inc"
void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
@ -111,8 +112,9 @@ void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
// precision). FIXME: Is there a better solution?
if (MI->getOpcode() == TargetOpcode::COPY_TO_REGCLASS)
return;
printInstruction(MI, O);
if (!printAliasInstr(MI, O))
printInstruction(MI, O);
printAnnotation(O, Annot);
}

4
llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
View File

@ -39,6 +39,10 @@ public:
void printInstruction(const MCInst *MI, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);
bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx,
raw_ostream &OS);
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printPredicateOperand(const MCInst *MI, unsigned OpNo,

2
llvm/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
; RUN: grep cntlzw
; RUN: grep cntlz
define i32 @foo() nounwind {
entry:

8
llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
View File

@ -9,13 +9,13 @@ entry:
; CHECK: mfcr [[T1:r[0-9]+]] ; cr2
; CHECK: lis [[T2:r[0-9]+]], 1
; CHECK: addi r3, r1, 72
; CHECK: rlwinm [[T1]], [[T1]], 8, 0, 31
; CHECK: rotlwi [[T1]], [[T1]], 8
; CHECK: ori [[T2]], [[T2]], 34540
; CHECK: stwx [[T1]], r1, [[T2]]
; CHECK: lis [[T3:r[0-9]+]], 1
; CHECK: mfcr [[T4:r[0-9]+]] ; cr3
; CHECK: ori [[T3]], [[T3]], 34536
; CHECK: rlwinm [[T4]], [[T4]], 12, 0, 31
; CHECK: rotlwi [[T4]], [[T4]], 12
; CHECK: stwx [[T4]], r1, [[T3]]
%x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
@ -28,12 +28,12 @@ return: ; preds = %entry
; CHECK: lis [[T1:r[0-9]+]], 1
; CHECK: ori [[T1]], [[T1]], 34536
; CHECK: lwzx [[T1]], r1, [[T1]]
; CHECK: rlwinm [[T1]], [[T1]], 20, 0, 31
; CHECK: rotlwi [[T1]], [[T1]], 20
; CHECK: mtcrf 16, [[T1]]
; CHECK: lis [[T1]], 1
; CHECK: ori [[T1]], [[T1]], 34540
; CHECK: lwzx [[T1]], r1, [[T1]]
; CHECK: rlwinm [[T1]], [[T1]], 24, 0, 31
; CHECK: rotlwi [[T1]], [[T1]], 24
; CHECK: mtcrf 32, [[T1]]
ret void
}

24
llvm/test/CodeGen/PowerPC/anon_aggr.ll
View File

@ -21,7 +21,7 @@ unequal:
}
; CHECK-LABEL: func1:
; CHECK: cmpld {{[0-9]+}}, 4, 5
; CHECK: cmpld {{([0-9]+,)?}}4, 5
; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]]
; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]]
; CHECK: ld 3, -[[OFFSET1]](1)
@ -31,7 +31,7 @@ unequal:
; DARWIN32: mr
; DARWIN32: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]]
; DARWIN32: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]]
; DARWIN32: cmplw cr{{[0-9]+}}, r[[REGA]], r[[REGB]]
; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGA]], r[[REGB]]
; DARWIN32: stw r[[REG1]], -[[OFFSET1:[0-9]+]]
; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
; DARWIN32: lwz r3, -[[OFFSET1]]
@ -41,7 +41,7 @@ unequal:
; DARWIN64: mr
; DARWIN64: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]]
; DARWIN64: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]]
; DARWIN64: cmpld cr{{[0-9]+}}, r[[REGA]], r[[REGB]]
; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REGB]]
; DARWIN64: std r[[REG1]], -[[OFFSET1:[0-9]+]]
; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]]
; DARWIN64: ld r3, -[[OFFSET1]]
@ -63,7 +63,7 @@ unequal:
; CHECK-LABEL: func2:
; CHECK: ld [[REG2:[0-9]+]], 72(1)
; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]]
; CHECK: cmpld {{([0-9]+,)?}}4, [[REG2]]
; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]]
; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]]
; CHECK: ld 3, -[[OFFSET2]](1)
@ -74,7 +74,7 @@ unequal:
; DARWIN32: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]])
; DARWIN32: mr
; DARWIN32: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]]
; DARWIN32: cmplw cr{{[0-9]+}}, r[[REGA]], r[[REG2]]
; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]]
; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]
; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
; DARWIN32: lwz r3, -[[OFFSET1]]
@ -84,7 +84,7 @@ unequal:
; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1)
; DARWIN64: mr
; DARWIN64: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]]
; DARWIN64: cmpld cr{{[0-9]+}}, r[[REGA]], r[[REG2]]
; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]]
; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]]
; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]]
; DARWIN64: ld r3, -[[OFFSET1]]
@ -108,7 +108,7 @@ unequal:
; CHECK-LABEL: func3:
; CHECK: ld [[REG3:[0-9]+]], 72(1)
; CHECK: ld [[REG4:[0-9]+]], 56(1)
; CHECK: cmpld {{[0-9]+}}, [[REG4]], [[REG3]]
; CHECK: cmpld {{([0-9]+,)?}}[[REG4]], [[REG3]]
; CHECK: std [[REG3]], -[[OFFSET1:[0-9]+]](1)
; CHECK: std [[REG4]], -[[OFFSET2:[0-9]+]](1)
; CHECK: ld 3, -[[OFFSET2]](1)
@ -119,7 +119,7 @@ unequal:
; DARWIN32: addi r[[REG2:[0-9]+]], r[[REGSP]], 24
; DARWIN32: lwz r[[REG3:[0-9]+]], 44(r[[REGSP]])
; DARWIN32: lwz r[[REG4:[0-9]+]], 32(r[[REGSP]])
; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]]
; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]
; DARWIN32: stw r[[REG4]], -[[OFFSET2:[0-9]+]]
; DARWIN32: lwz r3, -[[OFFSET2]]
@ -128,7 +128,7 @@ unequal:
; DARWIN64: _func3:
; DARWIN64: ld r[[REG3:[0-9]+]], 72(r1)
; DARWIN64: ld r[[REG4:[0-9]+]], 56(r1)
; DARWIN64: cmpld cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]]
; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]]
; DARWIN64: std r[[REG4]], -[[OFFSET2:[0-9]+]]
; DARWIN64: ld r3, -[[OFFSET2]]
@ -153,7 +153,7 @@ unequal:
; CHECK-LABEL: func4:
; CHECK: ld [[REG3:[0-9]+]], 136(1)
; CHECK: ld [[REG2:[0-9]+]], 120(1)
; CHECK: cmpld {{[0-9]+}}, [[REG2]], [[REG3]]
; CHECK: cmpld {{([0-9]+,)?}}[[REG2]], [[REG3]]
; CHECK: std [[REG3]], -[[OFFSET2:[0-9]+]](1)
; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]](1)
; CHECK: ld 3, -[[OFFSET1]](1)
@ -164,7 +164,7 @@ unequal:
; DARWIN32: addi r[[REG1:[0-9]+]], r1, 100
; DARWIN32: lwz r[[REG3:[0-9]+]], 108(r1)
; DARWIN32: mr r[[REG2:[0-9]+]], r[[REG4]]
; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]]
; DARWIN32: stw r[[REG2]], -[[OFFSET1:[0-9]+]]
; DARWIN32: stw r[[REG3]], -[[OFFSET2:[0-9]+]]
; DARWIN32: lwz r[[REG1]], -[[OFFSET1]]
@ -174,7 +174,7 @@ unequal:
; DARWIN64: ld r[[REG2:[0-9]+]], 120(r1)
; DARWIN64: ld r[[REG3:[0-9]+]], 136(r1)
; DARWIN64: mr r[[REG4:[0-9]+]], r[[REG2]]
; DARWIN64: cmpld cr{{[0-9]+}}, r[[REG2]], r[[REG3]]
; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REG2]], r[[REG3]]
; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]]
; DARWIN64: std r[[REG3]], -[[OFFSET2:[0-9]+]]
; DARWIN64: ld r3, -[[OFFSET1]]

2
llvm/test/CodeGen/PowerPC/asm-constraints.ll
View File

@ -31,7 +31,7 @@ entry:
; CHECK-LABEL: @foo
; CHECK: ld [[REG:[0-9]+]], 0(4)
; CHECK: cmpw 0, [[REG]], [[REG]]
; CHECK: cmpw [[REG]], [[REG]]
; CHECK: bne- 0, .Ltmp[[TMP:[0-9]+]]
; CHECK: .Ltmp[[TMP]]:
; CHECK: isync

4
llvm/test/CodeGen/PowerPC/atomic-2.ll
View File

@ -84,7 +84,7 @@ define void @atomic_store(i64* %mem, i64 %val) nounwind {
entry:
; CHECK: @atomic_store
store atomic i64 %val, i64* %mem release, align 64
; CHECK: sync 1
; CHECK: lwsync
; CHECK-NOT: stdcx
; CHECK: std
ret void
@ -96,7 +96,7 @@ entry:
%tmp = load atomic i64, i64* %mem acquire, align 64
; CHECK-NOT: ldarx
; CHECK: ld
; CHECK: sync 1
; CHECK: lwsync
ret i64 %tmp
}

8
llvm/test/CodeGen/PowerPC/atomics-fences.ll
View File

@ -5,16 +5,16 @@
; Fences
define void @fence_acquire() {
; CHECK-LABEL: fence_acquire
; CHECK: sync 1
; PPC440-NOT: sync 1
; CHECK: lwsync
; PPC440-NOT: lwsync
; PPC440: msync
fence acquire
ret void
}
define void @fence_release() {
; CHECK-LABEL: fence_release
; CHECK: sync 1
; PPC440-NOT: sync 1
; CHECK: lwsync
; PPC440-NOT: lwsync
; PPC440: msync
fence release
ret void

8
llvm/test/CodeGen/PowerPC/atomics-indexed.ll
View File

@ -11,7 +11,7 @@ define i8 @load_x_i8_seq_cst([100000 x i8]* %mem) {
; CHECK-LABEL: load_x_i8_seq_cst
; CHECK: sync 0
; CHECK: lbzx
; CHECK: sync 1
; CHECK: lwsync
%ptr = getelementptr inbounds [100000 x i8], [100000 x i8]* %mem, i64 0, i64 90000
%val = load atomic i8, i8* %ptr seq_cst, align 1
ret i8 %val
@ -19,7 +19,7 @@ define i8 @load_x_i8_seq_cst([100000 x i8]* %mem) {
define i16 @load_x_i16_acquire([100000 x i16]* %mem) {
; CHECK-LABEL: load_x_i16_acquire
; CHECK: lhzx
; CHECK: sync 1
; CHECK: lwsync
%ptr = getelementptr inbounds [100000 x i16], [100000 x i16]* %mem, i64 0, i64 90000
%val = load atomic i16, i16* %ptr acquire, align 2
ret i16 %val
@ -54,7 +54,7 @@ define void @store_x_i8_seq_cst([100000 x i8]* %mem) {
}
define void @store_x_i16_release([100000 x i16]* %mem) {
; CHECK-LABEL: store_x_i16_release
; CHECK: sync 1
; CHECK: lwsync
; CHECK: sthx
%ptr = getelementptr inbounds [100000 x i16], [100000 x i16]* %mem, i64 0, i64 90000
store atomic i16 42, i16* %ptr release, align 2
@ -71,7 +71,7 @@ define void @store_x_i32_monotonic([100000 x i32]* %mem) {
define void @store_x_i64_unordered([100000 x i64]* %mem) {
; CHECK-LABEL: store_x_i64_unordered
; CHECK-NOT: sync 0
; CHECK-NOT: sync 1
; CHECK-NOT: lwsync
; PPC32: __sync_
; PPC64-NOT: __sync_
; PPC64: stdx

24
llvm/test/CodeGen/PowerPC/atomics.ll
View File

@ -27,7 +27,7 @@ define i32 @load_i32_acquire(i32* %mem) {
; CHECK-LABEL: load_i32_acquire
; CHECK: lwz
%val = load atomic i32, i32* %mem acquire, align 4
; CHECK: sync 1
; CHECK: lwsync
ret i32 %val
}
define i64 @load_i64_seq_cst(i64* %mem) {
@ -37,7 +37,7 @@ define i64 @load_i64_seq_cst(i64* %mem) {
; PPC64-NOT: __sync_
; PPC64: ld
%val = load atomic i64, i64* %mem seq_cst, align 8
; CHECK: sync 1
; CHECK: lwsync
ret i64 %val
}
@ -58,7 +58,7 @@ define void @store_i16_monotonic(i16* %mem) {
}
define void @store_i32_release(i32* %mem) {
; CHECK-LABEL: store_i32_release
; CHECK: sync 1
; CHECK: lwsync
; CHECK: stw
store atomic i32 42, i32* %mem release, align 4
ret void
@ -78,7 +78,7 @@ define i8 @cas_strong_i8_sc_sc(i8* %mem) {
; CHECK-LABEL: cas_strong_i8_sc_sc
; CHECK: sync 0
%val = cmpxchg i8* %mem, i8 0, i8 1 seq_cst seq_cst
; CHECK: sync 1
; CHECK: lwsync
%loaded = extractvalue { i8, i1} %val, 0
ret i8 %loaded
}
@ -86,21 +86,21 @@ define i16 @cas_weak_i16_acquire_acquire(i16* %mem) {
; CHECK-LABEL: cas_weak_i16_acquire_acquire
;CHECK-NOT: sync
%val = cmpxchg weak i16* %mem, i16 0, i16 1 acquire acquire
; CHECK: sync 1
; CHECK: lwsync
%loaded = extractvalue { i16, i1} %val, 0
ret i16 %loaded
}
define i32 @cas_strong_i32_acqrel_acquire(i32* %mem) {
; CHECK-LABEL: cas_strong_i32_acqrel_acquire
; CHECK: sync 1
; CHECK: lwsync
%val = cmpxchg i32* %mem, i32 0, i32 1 acq_rel acquire
; CHECK: sync 1
; CHECK: lwsync
%loaded = extractvalue { i32, i1} %val, 0
ret i32 %loaded
}
define i64 @cas_weak_i64_release_monotonic(i64* %mem) {
; CHECK-LABEL: cas_weak_i64_release_monotonic
; CHECK: sync 1
; CHECK: lwsync
%val = cmpxchg weak i64* %mem, i64 0, i64 1 release monotonic
; CHECK-NOT: [sync ]
%loaded = extractvalue { i64, i1} %val, 0
@ -118,19 +118,19 @@ define i16 @xor_i16_seq_cst(i16* %mem, i16 %operand) {
; CHECK-LABEL: xor_i16_seq_cst
; CHECK: sync 0
%val = atomicrmw xor i16* %mem, i16 %operand seq_cst
; CHECK: sync 1
; CHECK: lwsync
ret i16 %val
}
define i32 @xchg_i32_acq_rel(i32* %mem, i32 %operand) {
; CHECK-LABEL: xchg_i32_acq_rel
; CHECK: sync 1
; CHECK: lwsync
%val = atomicrmw xchg i32* %mem, i32 %operand acq_rel
; CHECK: sync 1
; CHECK: lwsync
ret i32 %val
}
define i64 @and_i64_release(i64* %mem, i64 %operand) {
; CHECK-LABEL: and_i64_release
; CHECK: sync 1
; CHECK: lwsync
%val = atomicrmw and i64* %mem, i64 %operand release
; CHECK-NOT: [sync ]
ret i64 %val

32
llvm/test/CodeGen/PowerPC/bperm.ll
View File

@ -22,15 +22,15 @@ entry:
ret i64 %0
; CHECK-LABEL: @bs8
; CHECK-DAG: rldicl [[REG1:[0-9]+]], 3, 16, 0
; CHECK-DAG: rldicl [[REG2:[0-9]+]], 3, 8, 0
; CHECK-DAG: rldicl [[REG3:[0-9]+]], 3, 24, 0
; CHECK-DAG: rotldi [[REG1:[0-9]+]], 3, 16
; CHECK-DAG: rotldi [[REG2:[0-9]+]], 3, 8
; CHECK-DAG: rotldi [[REG3:[0-9]+]], 3, 24
; CHECK-DAG: rldimi [[REG2]], [[REG1]], 8, 48
; CHECK-DAG: rldicl [[REG4:[0-9]+]], 3, 32, 0
; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 32
; CHECK-DAG: rldimi [[REG2]], [[REG3]], 16, 40
; CHECK-DAG: rldicl [[REG5:[0-9]+]], 3, 48, 0
; CHECK-DAG: rotldi [[REG5:[0-9]+]], 3, 48
; CHECK-DAG: rldimi [[REG2]], [[REG4]], 24, 32
; CHECK-DAG: rldicl [[REG6:[0-9]+]], 3, 56, 0
; CHECK-DAG: rotldi [[REG6:[0-9]+]], 3, 56
; CHECK-DAG: rldimi [[REG2]], [[REG5]], 40, 16
; CHECK-DAG: rldimi [[REG2]], [[REG6]], 48, 8
; CHECK-DAG: rldimi [[REG2]], 3, 56, 0
@ -46,7 +46,7 @@ entry:
; CHECK-LABEL: @test1
; CHECK-DAG: li [[REG1:[0-9]+]], 11375
; CHECK-DAG: rldicl [[REG3:[0-9]+]], 4, 56, 0
; CHECK-DAG: rotldi [[REG3:[0-9]+]], 4, 56
; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 19
; CHECK: and 3, [[REG3]], [[REG2]]
; CHECK: blr
@ -60,7 +60,7 @@ entry:
; CHECK-LABEL: @test2
; CHECK-DAG: lis [[REG1:[0-9]+]], 474
; CHECK-DAG: rldicl [[REG5:[0-9]+]], 4, 58, 0
; CHECK-DAG: rotldi [[REG5:[0-9]+]], 4, 58
; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 3648
; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 25464
@ -76,7 +76,7 @@ entry:
; CHECK-LABEL: @test3
; CHECK-DAG: lis [[REG1:[0-9]+]], 170
; CHECK-DAG: rldicl [[REG4:[0-9]+]], 3, 34, 0
; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 34
; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 22861
; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 34
; CHECK: and 3, [[REG4]], [[REG3]]
@ -90,7 +90,7 @@ entry:
ret i64 %and
; CHECK-LABEL: @test4
; CHECK: rldicl [[REG1:[0-9]+]], 4, 49, 0
; CHECK: rotldi [[REG1:[0-9]+]], 4, 49
; CHECK: andis. 3, [[REG1]], 888
; CHECK: blr
}
@ -103,7 +103,7 @@ entry:
; CHECK-LABEL: @test5
; CHECK-DAG: lis [[REG1:[0-9]+]], 3703
; CHECK-DAG: rldicl [[REG4:[0-9]+]], 4, 12, 0
; CHECK-DAG: rotldi [[REG4:[0-9]+]], 4, 12
; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 35951
; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19
; CHECK: and 3, [[REG4]], [[REG3]]
@ -148,7 +148,7 @@ entry:
; CHECK-LABEL: @test8
; CHECK-DAG: lis [[REG1:[0-9]+]], 4
; CHECK-DAG: rldicl [[REG4:[0-9]+]], 3, 63, 0
; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 63
; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 60527
; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19
; CHECK: and 3, [[REG4]], [[REG3]]
@ -166,8 +166,8 @@ entry:
; CHECK-LABEL: @test9
; CHECK-DAG: lis [[REG1:[0-9]+]], 1440
; CHECK-DAG: rldicl [[REG5:[0-9]+]], 4, 62, 0
; CHECK-DAG: rldicl [[REG6:[0-9]+]], 4, 50, 0
; CHECK-DAG: rotldi [[REG5:[0-9]+]], 4, 62
; CHECK-DAG: rotldi [[REG6:[0-9]+]], 4, 50
; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 4
; CHECK-DAG: rldimi [[REG6]], [[REG5]], 53, 0
; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
@ -187,8 +187,8 @@ entry:
; CHECK-LABEL: @test10
; CHECK-DAG: lis [[REG1:[0-9]+]], 1
; CHECK-DAG: rldicl [[REG6:[0-9]+]], 3, 25, 0
; CHECK-DAG: rldicl [[REG7:[0-9]+]], 3, 37, 0
; CHECK-DAG: rotldi [[REG6:[0-9]+]], 3, 25
; CHECK-DAG: rotldi [[REG7:[0-9]+]], 3, 37
; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 8183
; CHECK-DAG: ori [[REG3:[0-9]+]], [[REG1]], 50017
; CHECK-DAG: sldi [[REG4:[0-9]+]], [[REG2]], 25

2
llvm/test/CodeGen/PowerPC/cmpb-ppc32.ll
View File

@ -17,7 +17,7 @@ entry:
; CHECK-LABEL: @test16
; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
; CHECK: rlwinm 3, [[REG1]], 0, 16, 31
; CHECK: clrlwi 3, [[REG1]], 16
; CHECK: blr
}

6
llvm/test/CodeGen/PowerPC/cmpb.ll
View File

@ -17,7 +17,7 @@ entry:
; CHECK-LABEL: @test16
; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
; CHECK: rldicl 3, [[REG1]], 0, 48
; CHECK: clrldi 3, [[REG1]], 48
; CHECK: blr
}
@ -73,7 +73,7 @@ entry:
; CHECK-LABEL: @test16p3
; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
; CHECK: rldicl [[REG2:[0-9]+]], [[REG1]], 0, 55
; CHECK: clrldi [[REG2:[0-9]+]], [[REG1]], 55
; CHECK: xori 3, [[REG2]], 1280
; CHECK: blr
}
@ -99,7 +99,7 @@ entry:
; CHECK-LABEL: @test32
; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
; CHECK: rldicl 3, [[REG1]], 0, 32
; CHECK: clrldi 3, [[REG1]], 32
; CHECK: blr
}

6
llvm/test/CodeGen/PowerPC/compare-simm.ll
View File

@ -1,7 +1,9 @@
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
; RUN: grep "cmpwi cr0, r3, -1"
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s
define i32 @test(i32 %x) nounwind {
; CHECK-LABEL: @test
; CHECK: cmpwi r3, -1
%c = icmp eq i32 %x, -1
br i1 %c, label %T, label %F
T:

6
llvm/test/CodeGen/PowerPC/crbit-asm.ll
View File

@ -12,7 +12,7 @@ entry:
; CHECK-LABEL: @testi1
; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
; CHECK-DAG: li [[REG1:[0-9]+]], 0
; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1
; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
; CHECK-DAG: li [[REG4:[0-9]+]], 1
@ -31,7 +31,7 @@ entry:
; CHECK-LABEL: @testi32
; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
; CHECK-DAG: li [[REG1:[0-9]+]], 0
; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1
; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
; CHECK-DAG: li [[REG4:[0-9]+]], -1
@ -47,7 +47,7 @@ entry:
; CHECK-LABEL: @testi8
; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
; CHECK-DAG: li [[REG1:[0-9]+]], 0
; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1
; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
; CHECK-DAG: li [[REG4:[0-9]+]], 1

2
llvm/test/CodeGen/PowerPC/crbits.ll
View File

@ -107,7 +107,7 @@ entry:
; CHECK-LABEL: @test6
; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
; CHECK-DAG: cmpwi {{[0-9]+}}, 5, -2
; CHECK-DAG: cror [[REG1:[0-9]+]], 1, 1
; CHECK-DAG: crmove [[REG1:[0-9]+]], 1
; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
; CHECK-DAG: li [[REG2:[0-9]+]], 1
; CHECK-DAG: crorc [[REG4:[0-9]+]], 1,

2
llvm/test/CodeGen/PowerPC/cttz.ll
View File

@ -6,7 +6,7 @@ declare i32 @llvm.cttz.i32(i32, i1)
define i32 @bar(i32 %x) {
entry:
; CHECK: @bar
; CHECK: cntlzw
; CHECK: cntlz
%tmp.1 = call i32 @llvm.cttz.i32( i32 %x, i1 true ) ; <i32> [#uses=1]
ret i32 %tmp.1
}

2
llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
View File

@ -201,7 +201,7 @@ define void @t12(i8 %a) uwtable ssp {
entry:
; ELF64: t12
%cmp = icmp ugt i8 %a, -113
; ELF64: rlwinm
; ELF64: clrlwi
; ELF64: cmplwi
br i1 %cmp, label %if.then, label %if.end

8
llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll
View File

@ -253,7 +253,7 @@ entry:
; ELF64LE: std
; ELF64LE: lfd
; ELF64LE: fcfidus
; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31
; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
; PPC970: std
; PPC970: lfd
; PPC970: fcfid
@ -277,7 +277,7 @@ entry:
; ELF64LE: std
; ELF64LE: lfd
; ELF64LE: fcfidus
; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
; PPC970: std
; PPC970: lfd
; PPC970: fcfid
@ -342,7 +342,7 @@ entry:
; ELF64LE: std
; ELF64LE: lfd
; ELF64LE: fcfidu
; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31
; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
; PPC970: std
; PPC970: lfd
; PPC970: fcfid
@ -365,7 +365,7 @@ entry:
; ELF64LE: std
; ELF64LE: lfd
; ELF64LE: fcfidu
; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
; PPC970: std
; PPC970: lfd
; PPC970: fcfid

4
llvm/test/CodeGen/PowerPC/fast-isel-ext.ll
View File

@ -5,14 +5,14 @@
define i32 @zext_8_32(i8 %a) nounwind ssp {
; ELF64: zext_8_32
%r = zext i8 %a to i32
; ELF64: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
ret i32 %r
}
define i32 @zext_16_32(i16 %a) nounwind ssp {
; ELF64: zext_16_32
%r = zext i16 %a to i32
; ELF64: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31
; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
ret i32 %r
}

2
llvm/test/CodeGen/PowerPC/i64_fp_round.ll
View File

@ -14,7 +14,7 @@ entry:
; CHECK: sradi [[REG1:[0-9]+]], 3, 53
; CHECK: addi [[REG2:[0-9]+]], [[REG1]], 1
; CHECK: cmpldi 0, [[REG2]], 1
; CHECK: cmpldi [[REG2]], 1
; CHECK: isel [[REG3:[0-9]+]], {{[0-9]+}}, 3, 1
; CHECK: std [[REG3]], -{{[0-9]+}}(1)

2
llvm/test/CodeGen/PowerPC/long-compare.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=ppc32 | grep cntlzw
; RUN: llc < %s -march=ppc32 | grep cntlz
; RUN: llc < %s -march=ppc32 | not grep xori
; RUN: llc < %s -march=ppc32 | not grep "li "
; RUN: llc < %s -march=ppc32 | not grep "mr "

4
llvm/test/CodeGen/PowerPC/ppc32-cyclecounter.ll
View File

@ -13,8 +13,8 @@ entry:
; CHECK: mfspr 3, 269
; CHECK: mfspr 4, 268
; CHECK: mfspr [[REG:[0-9]+]], 269
; CHECK: cmpw [[CR:[0-9]+]], 3, [[REG]]
; CHECK: bne [[CR]], .LBB
; CHECK: cmpw 3, [[REG]]
; CHECK: bne 0, .LBB
declare i64 @llvm.readcyclecounter()

2
llvm/test/CodeGen/PowerPC/ppc64-zext.ll
View File

@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-linux"
define i64 @fun(i32 %arg32) nounwind {
entry:
; CHECK: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32
; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
%o = zext i32 %arg32 to i64
ret i64 %o
}

2
llvm/test/CodeGen/PowerPC/rlwimi-and.ll
View File

@ -29,7 +29,7 @@ codeRepl17: ; preds = %codeRepl4
unreachable
; CHECK: @test
; CHECK: rlwinm [[R1:[0-9]+]], {{[0-9]+}}, 0, 31, 31
; CHECK: clrlwi [[R1:[0-9]+]], {{[0-9]+}}, 31
; CHECK: rlwimi [[R1]], {{[0-9]+}}, 8, 23, 23
codeRepl29: ; preds = %codeRepl1

5
llvm/test/CodeGen/PowerPC/rotl-2.ll
View File

@ -1,5 +1,6 @@
; RUN: llc < %s -march=ppc32 | grep rlwinm | count 4
; RUN: llc < %s -march=ppc32 | grep rlwnm | count 2
; RUN: llc < %s -march=ppc32 | grep rotlwi | count 2
; RUN: llc < %s -march=ppc32 | grep clrlwi | count 2
; RUN: llc < %s -march=ppc32 | grep rotlw | count 4
; RUN: llc < %s -march=ppc32 | not grep or
define i32 @rotl32(i32 %A, i8 %Amt) nounwind {

4
llvm/test/CodeGen/PowerPC/rotl-64.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -march=ppc64 | grep rldicl
; RUN: llc < %s -march=ppc64 | grep rldcl
; RUN: llc < %s -march=ppc64 | grep rotld
; RUN: llc < %s -march=ppc64 | grep rotldi
; PR1613
define i64 @t1(i64 %A) {

6
llvm/test/CodeGen/PowerPC/rotl.ll
View File

@ -1,5 +1,7 @@
; RUN: llc < %s -march=ppc32 | grep rlwnm | count 2
; RUN: llc < %s -march=ppc32 | grep rlwinm | count 2
; RUN: llc < %s -march=ppc32 | grep rotrw: | count 1
; RUN: llc < %s -march=ppc32 | grep rotlw: | count 1
; RUN: llc < %s -march=ppc32 | grep rotlwi: | count 1
; RUN: llc < %s -march=ppc32 | grep rotrwi: | count 1
define i32 @rotlw(i32 %x, i32 %sh) {
entry:

2
llvm/test/CodeGen/PowerPC/sdag-ppcf128.ll
View File

@ -5,7 +5,7 @@
define fastcc void @_D3std4math4sqrtFNaNbNfcZc() {
entry:
br i1 undef, label %if, label %else
; CHECK: cmplwi 0, 3, 0
; CHECK: cmplwi 3, 0
if: ; preds = %entry
store { ppc_fp128, ppc_fp128 } zeroinitializer, { ppc_fp128, ppc_fp128 }* undef
ret void

2
llvm/test/CodeGen/PowerPC/seteq-0.ll
View File

@ -5,7 +5,7 @@ define i32 @eq0(i32 %a) {
%tmp.2 = zext i1 %tmp.1 to i32 ; <i32> [#uses=1]
ret i32 %tmp.2
; CHECK: cntlzw [[REG:r[0-9]+]], r3
; CHECK: cntlz [[REG:r[0-9]+]], r3
; CHECK: rlwinm r3, [[REG]], 27, 31, 31
; CHECK: blr
}

18
llvm/test/CodeGen/PowerPC/stack-realign.ll
View File

@ -30,7 +30,7 @@ entry:
; CHECK-LABEL: @goo
; CHECK-DAG: mflr 0
; CHECK-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59
; CHECK-DAG: clrldi [[REG:[0-9]+]], 1, 59
; CHECK-DAG: std 30, -16(1)
; CHECK-DAG: mr 30, 1
; CHECK-DAG: std 0, 16(1)
@ -52,7 +52,7 @@ entry:
; CHECK-FP-LABEL: @goo
; CHECK-FP-DAG: mflr 0
; CHECK-FP-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59
; CHECK-FP-DAG: clrldi [[REG:[0-9]+]], 1, 59
; CHECK-FP-DAG: std 31, -8(1)
; CHECK-FP-DAG: std 30, -16(1)
; CHECK-FP-DAG: mr 30, 1
@ -78,7 +78,7 @@ entry:
; CHECK-32-LABEL: @goo
; CHECK-32-DAG: mflr 0
; CHECK-32-DAG: rlwinm [[REG:[0-9]+]], 1, 0, 27, 31
; CHECK-32-DAG: clrlwi [[REG:[0-9]+]], 1, 27
; CHECK-32-DAG: stw 30, -8(1)
; CHECK-32-DAG: mr 30, 1
; CHECK-32-DAG: stw 0, 4(1)
@ -87,7 +87,7 @@ entry:
; CHECK-32-PIC-LABEL: @goo
; CHECK-32-PIC-DAG: mflr 0
; CHECK-32-PIC-DAG: rlwinm [[REG:[0-9]+]], 1, 0, 27, 31
; CHECK-32-PIC-DAG: clrlwi [[REG:[0-9]+]], 1, 27
; CHECK-32-PIC-DAG: stw 29, -12(1)
; CHECK-32-PIC-DAG: mr 29, 1
; CHECK-32-PIC-DAG: stw 0, 4(1)
@ -113,7 +113,7 @@ entry:
; CHECK-LABEL: @hoo
; CHECK-DAG: lis [[REG1:[0-9]+]], -13
; CHECK-DAG: rldicl [[REG3:[0-9]+]], 1, 0, 59
; CHECK-DAG: clrldi [[REG3:[0-9]+]], 1, 59
; CHECK-DAG: mflr 0
; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51808
; CHECK-DAG: std 30, -16(1)
@ -129,7 +129,7 @@ entry:
; CHECK-32-LABEL: @hoo
; CHECK-32-DAG: lis [[REG1:[0-9]+]], -13
; CHECK-32-DAG: rlwinm [[REG3:[0-9]+]], 1, 0, 27, 31
; CHECK-32-DAG: clrlwi [[REG3:[0-9]+]], 1, 27
; CHECK-32-DAG: mflr 0
; CHECK-32-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
; CHECK-32-DAG: stw 30, -8(1)
@ -143,7 +143,7 @@ entry:
; CHECK-32-PIC-LABEL: @hoo
; CHECK-32-PIC-DAG: lis [[REG1:[0-9]+]], -13
; CHECK-32-PIC-DAG: rlwinm [[REG3:[0-9]+]], 1, 0, 27, 31
; CHECK-32-PIC-DAG: clrlwi [[REG3:[0-9]+]], 1, 27
; CHECK-32-PIC-DAG: mflr 0
; CHECK-32-PIC-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
; CHECK-32-PIC-DAG: stw 29, -12(1)
@ -175,7 +175,7 @@ entry:
; CHECK-LABEL: @loo
; CHECK-DAG: mflr 0
; CHECK-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59
; CHECK-DAG: clrldi [[REG:[0-9]+]], 1, 59
; CHECK-DAG: std 30, -32(1)
; CHECK-DAG: mr 30, 1
; CHECK-DAG: std 0, 16(1)
@ -191,7 +191,7 @@ entry:
; CHECK-FP-LABEL: @loo
; CHECK-FP-DAG: mflr 0
; CHECK-FP-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59
; CHECK-FP-DAG: clrldi [[REG:[0-9]+]], 1, 59
; CHECK-FP-DAG: std 31, -24(1)
; CHECK-FP-DAG: std 30, -32(1)
; CHECK-FP-DAG: mr 30, 1

2
llvm/test/CodeGen/PowerPC/subreg-postra-2.ll
View File

@ -160,7 +160,7 @@ while.end418: ; preds = %wait_on_buffer.exit
; CHECK-LABEL: @jbd2_journal_commit_transaction
; CHECK: andi.
; CHECK: cror [[REG:[0-9]+]], 1, 1
; CHECK: crmove [[REG:[0-9]+]], 1
; CHECK: stdcx.
; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]

2
llvm/test/CodeGen/PowerPC/subreg-postra.ll
View File

@ -143,7 +143,7 @@ wait_on_buffer.exit1319: ; preds = %while.body392
; CHECK-LABEL: @jbd2_journal_commit_transaction
; CHECK: andi.
; CHECK: cror [[REG:[0-9]+]], 1, 1
; CHECK: crmove [[REG:[0-9]+]], 1
; CHECK: stdcx.
; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]

2
llvm/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -mcpu=pwr8 -mattr=+vsx -O2 -mtriple=powerpc64le-unknown-linux-gnu < %s > %t
; RUN: grep lxvd2x < %t | count 18
; RUN: grep stxvd2x < %t | count 18
; RUN: grep xxpermdi < %t | count 36
; RUN: grep xxswapd < %t | count 36
@vf = global <4 x float> <float -1.500000e+00, float 2.500000e+00, float -3.500000e+00, float 4.500000e+00>, align 16
@vd = global <2 x double> <double 3.500000e+00, double -7.500000e+00>, align 16

2
llvm/test/CodeGen/PowerPC/vsx-ldst.ll
View File

@ -12,7 +12,7 @@
; RUN: llc -mcpu=pwr8 -mattr=+vsx -O2 -mtriple=powerpc64le-unknown-linux-gnu < %s > %t
; RUN: grep lxvd2x < %t | count 6
; RUN: grep stxvd2x < %t | count 6
; RUN: grep xxpermdi < %t | count 12
; RUN: grep xxswapd < %t | count 12
@vsi = global <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, align 16
@vui = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16

14
llvm/test/CodeGen/PowerPC/vsx.ll
View File

@ -733,7 +733,7 @@ define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {
ret <2 x double> %v
; CHECK-LABEL: @test51
; CHECK: xxpermdi 34, 34, 34, 0
; CHECK: xxspltd 34, 34, 0
; CHECK: blr
}
@ -742,7 +742,7 @@ define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {
ret <2 x double> %v
; CHECK-LABEL: @test52
; CHECK: xxpermdi 34, 34, 35, 0
; CHECK: xxmrghd 34, 34, 35
; CHECK: blr
}
@ -751,7 +751,7 @@ define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {
ret <2 x double> %v
; CHECK-LABEL: @test53
; CHECK: xxpermdi 34, 35, 34, 0
; CHECK: xxmrghd 34, 35, 34
; CHECK: blr
}
@ -769,7 +769,7 @@ define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {
ret <2 x double> %v
; CHECK-LABEL: @test55
; CHECK: xxpermdi 34, 34, 35, 3
; CHECK: xxmrgld 34, 34, 35
; CHECK: blr
}
@ -778,7 +778,7 @@ define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
ret <2 x i64> %v
; CHECK-LABEL: @test56
; CHECK: xxpermdi 34, 34, 35, 3
; CHECK: xxmrgld 34, 34, 35
; CHECK: blr
}
@ -843,11 +843,11 @@ define double @test64(<2 x double> %a) {
ret double %v
; CHECK-REG-LABEL: @test64
; CHECK-REG: xxpermdi 1, 34, 34, 2
; CHECK-REG: xxswapd 1, 34
; CHECK-REG: blr
; CHECK-FISL-LABEL: @test64
; CHECK-FISL: xxpermdi 34, 34, 34, 2
; CHECK-FISL: xxswapd 34, 34
; CHECK-FISL: xxlor 0, 34, 34
; CHECK-FISL: fmr 1, 0
; CHECK-FISL: blr

16
llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
View File

@ -9,8 +9,8 @@ define <2 x double> @testi0(<2 x double>* %p1, double* %p2) {
; CHECK-LABEL: testi0
; CHECK: lxvd2x 0, 0, 3
; CHECK: lxsdx 34, 0, 4
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 1, 34, 34, 0
; CHECK: xxswapd 0, 0
; CHECK: xxspltd 1, 34, 0
; CHECK: xxpermdi 34, 0, 1, 1
}
@ -23,9 +23,9 @@ define <2 x double> @testi1(<2 x double>* %p1, double* %p2) {
; CHECK-LABEL: testi1
; CHECK: lxvd2x 0, 0, 3
; CHECK: lxsdx 34, 0, 4
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 1, 34, 34, 0
; CHECK: xxpermdi 34, 1, 0, 3
; CHECK: xxswapd 0, 0
; CHECK: xxspltd 1, 34, 0
; CHECK: xxmrgld 34, 1, 0
}
define double @teste0(<2 x double>* %p1) {
@ -37,8 +37,8 @@ define double @teste0(<2 x double>* %p1) {
; CHECK-LABEL: teste0
; CHECK: lxvd2x 0, 0, 3
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 1, 0, 0, 2
; CHECK: xxswapd 0, 0
; CHECK: xxswapd 1, 0
}
define double @teste1(<2 x double>* %p1) {
@ -48,5 +48,5 @@ define double @teste1(<2 x double>* %p1) {
; CHECK-LABEL: teste1
; CHECK: lxvd2x 0, 0, 3
; CHECK: xxpermdi 1, 0, 0, 2
; CHECK: xxswapd 1, 0
}

68
llvm/test/CodeGen/PowerPC/vsx_shuffle_le.ll
View File

@ -8,8 +8,8 @@ define <2 x double> @test00(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: test00
; CHECK: lxvd2x 0, 0, 3
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 34, 0, 0, 3
; CHECK: xxswapd 0, 0
; CHECK: xxspltd 34, 0, 1
}
define <2 x double> @test01(<2 x double>* %p1, <2 x double>* %p2) {
@ -20,7 +20,7 @@ define <2 x double> @test01(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: test01
; CHECK: lxvd2x 0, 0, 3
; CHECK: xxpermdi 34, 0, 0, 2
; CHECK: xxswapd 34, 0
}
define <2 x double> @test02(<2 x double>* %p1, <2 x double>* %p2) {
@ -32,9 +32,9 @@ define <2 x double> @test02(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: @test02
; CHECK: lxvd2x 0, 0, 3
; CHECK: lxvd2x 1, 0, 4
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 1, 1, 1, 2
; CHECK: xxpermdi 34, 1, 0, 3
; CHECK: xxswapd 0, 0
; CHECK: xxswapd 1, 1
; CHECK: xxmrgld 34, 1, 0
}
define <2 x double> @test03(<2 x double>* %p1, <2 x double>* %p2) {
@ -46,8 +46,8 @@ define <2 x double> @test03(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: @test03
; CHECK: lxvd2x 0, 0, 3
; CHECK: lxvd2x 1, 0, 4
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 1, 1, 1, 2
; CHECK: xxswapd 0, 0
; CHECK: xxswapd 1, 1
; CHECK: xxpermdi 34, 1, 0, 1
}
@ -59,8 +59,8 @@ define <2 x double> @test10(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: @test10
; CHECK: lxvd2x 0, 0, 3
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 34, 0, 0, 2
; CHECK: xxswapd 0, 0
; CHECK: xxswapd 34, 0
}
define <2 x double> @test11(<2 x double>* %p1, <2 x double>* %p2) {
@ -71,8 +71,8 @@ define <2 x double> @test11(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: @test11
; CHECK: lxvd2x 0, 0, 3
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 34, 0, 0, 0
; CHECK: xxswapd 0, 0
; CHECK: xxspltd 34, 0, 0
}
define <2 x double> @test12(<2 x double>* %p1, <2 x double>* %p2) {
@ -84,8 +84,8 @@ define <2 x double> @test12(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: @test12
; CHECK: lxvd2x 0, 0, 3
; CHECK: lxvd2x 1, 0, 4
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 1, 1, 1, 2
; CHECK: xxswapd 0, 0
; CHECK: xxswapd 1, 1
; CHECK: xxpermdi 34, 1, 0, 2
}
@ -98,9 +98,9 @@ define <2 x double> @test13(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: @test13
; CHECK: lxvd2x 0, 0, 3
; CHECK: lxvd2x 1, 0, 4
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 1, 1, 1, 2
; CHECK: xxpermdi 34, 1, 0, 0
; CHECK: xxswapd 0, 0
; CHECK: xxswapd 1, 1
; CHECK: xxmrghd 34, 1, 0
}
define <2 x double> @test20(<2 x double>* %p1, <2 x double>* %p2) {
@ -112,9 +112,9 @@ define <2 x double> @test20(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: @test20
; CHECK: lxvd2x 0, 0, 3
; CHECK: lxvd2x 1, 0, 4
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 1, 1, 1, 2
; CHECK: xxpermdi 34, 0, 1, 3
; CHECK: xxswapd 0, 0
; CHECK: xxswapd 1, 1
; CHECK: xxmrgld 34, 0, 1
}
define <2 x double> @test21(<2 x double>* %p1, <2 x double>* %p2) {
@ -126,8 +126,8 @@ define <2 x double> @test21(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: @test21
; CHECK: lxvd2x 0, 0, 3
; CHECK: lxvd2x 1, 0, 4
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 1, 1, 1, 2
; CHECK: xxswapd 0, 0
; CHECK: xxswapd 1, 1
; CHECK: xxpermdi 34, 0, 1, 1
}
@ -139,8 +139,8 @@ define <2 x double> @test22(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: @test22
; CHECK: lxvd2x 0, 0, 4
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 34, 0, 0, 3
; CHECK: xxswapd 0, 0
; CHECK: xxspltd 34, 0, 1
}
define <2 x double> @test23(<2 x double>* %p1, <2 x double>* %p2) {
@ -151,7 +151,7 @@ define <2 x double> @test23(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: @test23
; CHECK: lxvd2x 0, 0, 4
; CHECK: xxpermdi 34, 0, 0, 2
; CHECK: xxswapd 34, 0
}
define <2 x double> @test30(<2 x double>* %p1, <2 x double>* %p2) {
@ -163,8 +163,8 @@ define <2 x double> @test30(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: @test30
; CHECK: lxvd2x 0, 0, 3
; CHECK: lxvd2x 1, 0, 4
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 1, 1, 1, 2
; CHECK: xxswapd 0, 0
; CHECK: xxswapd 1, 1
; CHECK: xxpermdi 34, 0, 1, 2
}
@ -177,9 +177,9 @@ define <2 x double> @test31(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: @test31
; CHECK: lxvd2x 0, 0, 3
; CHECK: lxvd2x 1, 0, 4
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 1, 1, 1, 2
; CHECK: xxpermdi 34, 0, 1, 0
; CHECK: xxswapd 0, 0
; CHECK: xxswapd 1, 1
; CHECK: xxmrghd 34, 0, 1
}
define <2 x double> @test32(<2 x double>* %p1, <2 x double>* %p2) {
@ -190,8 +190,8 @@ define <2 x double> @test32(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: @test32
; CHECK: lxvd2x 0, 0, 4
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 34, 0, 0, 2
; CHECK: xxswapd 0, 0
; CHECK: xxswapd 34, 0
}
define <2 x double> @test33(<2 x double>* %p1, <2 x double>* %p2) {
@ -202,6 +202,6 @@ define <2 x double> @test33(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: @test33
; CHECK: lxvd2x 0, 0, 4
; CHECK: xxpermdi 0, 0, 0, 2
; CHECK: xxpermdi 34, 0, 0, 0
; CHECK: xxswapd 0, 0
; CHECK: xxspltd 34, 0, 0
}

8
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-4xx.txt
View File

@ -5,14 +5,14 @@
# CHECK: mtdcr 178, 3
0x7c 0x72 0x2b 0x86
# CHECK: tlbre 2, 3, 0
# CHECK: tlbrehi 2, 3
0x7c 0x43 0x07 0x64
# CHECK: tlbre 2, 3, 1
# CHECK: tlbrelo 2, 3
0x7c 0x43 0x0f 0x64
# CHECK: tlbwe 2, 3, 0
# CHECK: tlbwehi 2, 3
0x7c 0x43 0x07 0xa4
# CHECK: tlbwe 2, 3, 1
# CHECK: tlbwelo 2, 3
0x7c 0x43 0x0f 0xa4
# CHECK: tlbsx 2, 3, 1

16
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
View File

@ -27,13 +27,13 @@
# CHECK: stdcx. 2, 3, 4
0x7c 0x43 0x21 0xad
# CHECK: sync 2
# CHECK: ptesync
0x7c 0x40 0x04 0xac
# CHECK: eieio
0x7c 0x00 0x06 0xac
# CHECK: wait 2
# CHECK: waitimpl
0x7c 0x40 0x00 0x7c
# CHECK: mbar 1
@ -72,19 +72,19 @@
# CHECK: sync 0
0x7c 0x00 0x04 0xac
# CHECK: sync 1
# CHECK: lwsync
0x7c 0x20 0x04 0xac
# CHECK: sync 2
# CHECK: ptesync
0x7c 0x40 0x04 0xac
# CHECK: wait 0
# CHECK: wait
0x7c 0x00 0x00 0x7c
# CHECK: wait 1
# CHECK: waitrsv
0x7c 0x20 0x00 0x7c
# CHECK: wait 2
# CHECK: waitimpl
0x7c 0x40 0x00 0x7c
# CHECK: mftb 2, 123
@ -93,6 +93,6 @@
# CHECK: mftb 2, 268
0x7c 0x4c 0x42 0xe6
# CHECK: mftb 2, 269
# CHECK: mftbu 2
0x7c 0x4d 0x42 0xe6

10
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt
View File

@ -1,6 +1,6 @@
# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s
# CHECK: mtmsr 4, 0
# CHECK: mtmsr 4
0x7c 0x80 0x01 0x24
# CHECK: mtmsr 4, 1
@ -9,7 +9,7 @@
# CHECK: mfmsr 4
0x7c 0x80 0x00 0xa6
# CHECK: mtmsrd 4, 0
# CHECK: mtmsrd 4
0x7c 0x80 0x01 0x64
# CHECK: mtmsrd 4, 1
@ -60,7 +60,7 @@
# CHECK: mtspr 22, 4
0x7c 0x96 0x03 0xa6
# CHECK: mfspr 4, 287
# CHECK: mfpvr 4
0x7c 0x9f 0x42 0xa6
# CHECK: mfspr 4, 25
@ -99,10 +99,10 @@
# CHECK: tlbiel 4
0x7c 0x00 0x22 0x24
# CHECK: tlbie 4,0
# CHECK: tlbie 4
0x7c 0x00 0x22 0x64
# CHECK: tlbie 4,0
# CHECK: tlbie 4
0x7c 0x00 0x22 0x64
# CHECK: rfi

854
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
View File

File diff suppressed because it is too large Load Diff

22
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
View File

@ -19,25 +19,25 @@
# CHECK: bclr 4, 10, 3
0x4c 0x8a 0x18 0x20
# CHECK: bclr 4, 10, 0
# CHECK: bclr 4, 10
0x4c 0x8a 0x00 0x20
# CHECK: bclrl 4, 10, 3
0x4c 0x8a 0x18 0x21
# CHECK: bclrl 4, 10, 0
# CHECK: bclrl 4, 10
0x4c 0x8a 0x00 0x21
# CHECK: bcctr 4, 10, 3
0x4c 0x8a 0x1c 0x20
# CHECK: bcctr 4, 10, 0
# CHECK: bcctr 4, 10
0x4c 0x8a 0x04 0x20
# CHECK: bcctrl 4, 10, 3
0x4c 0x8a 0x1c 0x21
# CHECK: bcctrl 4, 10, 0
# CHECK: bcctrl 4, 10
0x4c 0x8a 0x04 0x21
# CHECK: crand 2, 3, 4
@ -70,7 +70,7 @@
# CHECK: sc 1
0x44 0x00 0x00 0x22
# CHECK: sc 0
# CHECK: sc
0x44 0x00 0x00 0x02
# CHECK: lbz 2, 128(4)
@ -406,16 +406,16 @@
# CHECK: cmplw 2, 3, 4
0x7d 0x03 0x20 0x40
# CHECK: twi 2, 3, 4
# CHECK: twllti 3, 4
0x0c 0x43 0x00 0x04
# CHECK: tw 2, 3, 4
# CHECK: twllt 3, 4
0x7c 0x43 0x20 0x08
# CHECK: tdi 2, 3, 4
# CHECK: tdllti 3, 4
0x08 0x43 0x00 0x04
# CHECK: td 2, 3, 4
# CHECK: tdllt 3, 4
0x7c 0x43 0x20 0x88
# CHECK: isel 2, 3, 4, 5
@ -499,10 +499,10 @@
# CHECK: extsh. 2, 3
0x7c 0x62 0x07 0x35
# CHECK: cntlzw 2, 3
# CHECK: cntlz 2, 3
0x7c 0x62 0x00 0x34
# CHECK: cntlzw. 2, 3
# CHECK: cntlz. 2, 3
0x7c 0x62 0x00 0x35
# CHECK: popcntw 2, 3

4
llvm/test/MC/Disassembler/PowerPC/ppc64-operands.txt
View File

@ -85,10 +85,10 @@
0x48 0x00 0x04 0x02
# FIXME: decode as beq 0, .+1024
# CHECK: bc 12, 2, .+1024
# CHECK: bt 2, .+1024
0x41 0x82 0x04 0x00
# FIXME: decode as beqa 0, 1024
# CHECK: bca 12, 2, 1024
# CHECK: bta 2, 1024
0x41 0x82 0x04 0x02

36
llvm/test/MC/Disassembler/PowerPC/qpx.txt
View File

@ -9,12 +9,10 @@
# CHECK: qvfadds 3, 4, 5
0x00 0x64 0x28 0x2a
# FIXME: decode as qvfandc 3, 4, 5
# CHECK: qvflogical 3, 4, 5, 4
# CHECK: qvfandc 3, 4, 5
0x10 0x64 0x2a 0x08
# FIXME: decode as qvfand 3, 4, 5
# CHECK: qvflogical 3, 4, 5, 1
# CHECK: qvfand 3, 4, 5
0x10 0x64 0x28 0x88
# CHECK: qvfcfid 3, 5
@ -29,15 +27,13 @@
# CHECK: qvfcfidus 3, 5
0x00 0x60 0x2f 0x9c
# FIXME: decode as qvfclr 3
# CHECK: qvflogical 3, 3, 3, 0
# CHECK: qvfclr 3
0x10 0x63 0x18 0x08
# CHECK: qvfcpsgn 3, 4, 5
0x10 0x64 0x28 0x10
# FIXME: decode as qvfctfb 3, 4
# CHECK: qvflogical 3, 4, 4, 5
# CHECK: qvfctfb 3, 4
0x10 0x64 0x22 0x88
# CHECK: qvfctid 3, 5
@ -64,8 +60,7 @@
# CHECK: qvfctiwz 3, 5
0x10 0x60 0x28 0x1e
# FIXME: decode as qvfequ 3, 4, 5
# CHECK: qvflogical 3, 4, 5, 9
# CHECK: qvfequ 3, 4, 5
0x10 0x64 0x2c 0x88
# CHECK: qvflogical 3, 4, 5, 12
@ -95,8 +90,7 @@
# CHECK: qvfnabs 3, 5
0x10 0x60 0x29 0x10
# FIXME: decode as qvfnand 3, 4, 5
# CHECK: qvflogical 3, 4, 5, 14
# CHECK: qvfnand 3, 4, 5
0x10 0x64 0x2f 0x08
# CHECK: qvfneg 3, 5
@ -114,20 +108,16 @@
# CHECK: qvfnmsubs 3, 4, 6, 5
0x00 0x64 0x29 0xbc
# FIXME: decode as qvfnor 3, 4, 5
# CHECK: qvflogical 3, 4, 5, 8
# CHECK: qvfnor 3, 4, 5
0x10 0x64 0x2c 0x08
# FIXME: decode as qvfnot 3, 4
# CHECK: qvflogical 3, 4, 4, 10
# CHECK: qvfnot 3, 4
0x10 0x64 0x25 0x08
# FIXME: decode as qvforc 3, 4, 5
# CHECK: qvflogical 3, 4, 5, 13
# CHECK: qvforc 3, 4, 5
0x10 0x64 0x2e 0x88
# FIXME: decode as qvfor 3, 4, 5
# CHECK: qvflogical 3, 4, 5, 7
# CHECK: qvfor 3, 4, 5
0x10 0x64 0x2b 0x88
# CHECK: qvfperm 3, 4, 5, 6
@ -163,8 +153,7 @@
# CHECK: qvfsel 3, 4, 6, 5
0x10 0x64 0x29 0xae
# FIXME: decode as qvfset 3
# CHECK: qvflogical 3, 3, 3, 15
# CHECK: qvfset 3
0x10 0x63 0x1f 0x88
# CHECK: qvfsub 3, 4, 5
@ -185,8 +174,7 @@
# CHECK: qvfxmuls 3, 4, 6
0x00 0x64 0x01 0xa2
# FIXME: decode as qvfxor 3, 4, 5
# CHECK: qvflogical 3, 4, 5, 6
# CHECK: qvfxor 3, 4, 5
0x10 0x64 0x2b 0x08
# CHECK: qvfxxcpnmadd 3, 4, 6, 5

18
llvm/test/MC/Disassembler/PowerPC/vsx.txt
View File

@ -273,12 +273,10 @@
# CHECK: xvminsp 7, 63, 27
0xf0 0xff 0xde 0x44
# FIXME: decode as xvmovdp 7, 63
# CHECK: xvcpsgndp 7, 63, 63
# CHECK: xvmovdp 7, 63
0xf0 0xff 0xff 0x86
# FIXME: decode as xvmovsp 7, 63
# CHECK: xvcpsgnsp 7, 63, 63
# CHECK: xvmovsp 7, 63
0xf0 0xff 0xfe 0x86
# CHECK: xvmsubadp 7, 63, 27
@ -425,15 +423,13 @@
# CHECK: xxlxor 7, 63, 27
0xf0 0xff 0xdc 0xd4
# FIXME: decode as xxmrghd 7, 63, 27
# CHECK: xxpermdi 7, 63, 27, 0
# CHECK: xxmrghd 7, 63, 27
0xf0 0xff 0xd8 0x54
# CHECK: xxmrghw 7, 63, 27
0xf0 0xff 0xd8 0x94
# FIXME: decode as xxmrgld 7, 63, 27
# CHECK: xxpermdi 7, 63, 27, 3
# CHECK: xxmrgld 7, 63, 27
0xf0 0xff 0xdb 0x54
# CHECK: xxmrglw 7, 63, 27
@ -448,15 +444,13 @@
# CHECK: xxsldwi 7, 63, 27, 1
0xf0 0xff 0xd9 0x14
# FIXME: decode as xxspltd 7, 63, 1
# CHECK: xxpermdi 7, 63, 63, 3
# CHECK: xxspltd 7, 63, 1
0xf0 0xff 0xfb 0x56
# CHECK: xxspltw 7, 27, 3
0xf0 0xe3 0xda 0x90
# FIXME: decode as xxswapd 7, 63
# CHECK: xxpermdi 7, 63, 63, 2
# CHECK: xxswapd 7, 63
0xf0 0xff 0xfa 0x56
# CHECK: mfvsrd 3, 0

168
llvm/test/MC/PowerPC/ppc64-encoding-4xx.s
View File

@ -10,30 +10,30 @@
# CHECK-LE: mtdcr 178, 3 # encoding: [0x86,0x2b,0x72,0x7c]
mtdcr 178,3
# CHECK-BE: tlbre 2, 3, 0 # encoding: [0x7c,0x43,0x07,0x64]
# CHECK-LE: tlbre 2, 3, 0 # encoding: [0x64,0x07,0x43,0x7c]
# CHECK-BE: tlbrehi 2, 3 # encoding: [0x7c,0x43,0x07,0x64]
# CHECK-LE: tlbrehi 2, 3 # encoding: [0x64,0x07,0x43,0x7c]
tlbre %r2, %r3, 0
# CHECK-BE: tlbre 2, 3, 1 # encoding: [0x7c,0x43,0x0f,0x64]
# CHECK-LE: tlbre 2, 3, 1 # encoding: [0x64,0x0f,0x43,0x7c]
# CHECK-BE: tlbrelo 2, 3 # encoding: [0x7c,0x43,0x0f,0x64]
# CHECK-LE: tlbrelo 2, 3 # encoding: [0x64,0x0f,0x43,0x7c]
tlbre %r2, %r3, 1
# CHECK-BE: tlbre 2, 3, 0 # encoding: [0x7c,0x43,0x07,0x64]
# CHECK-LE: tlbre 2, 3, 0 # encoding: [0x64,0x07,0x43,0x7c]
# CHECK-BE: tlbrehi 2, 3 # encoding: [0x7c,0x43,0x07,0x64]
# CHECK-LE: tlbrehi 2, 3 # encoding: [0x64,0x07,0x43,0x7c]
tlbrehi %r2, %r3
# CHECK-BE: tlbre 2, 3, 1 # encoding: [0x7c,0x43,0x0f,0x64]
# CHECK-LE: tlbre 2, 3, 1 # encoding: [0x64,0x0f,0x43,0x7c]
# CHECK-BE: tlbrelo 2, 3 # encoding: [0x7c,0x43,0x0f,0x64]
# CHECK-LE: tlbrelo 2, 3 # encoding: [0x64,0x0f,0x43,0x7c]
tlbrelo %r2, %r3
# CHECK-BE: tlbwe 2, 3, 0 # encoding: [0x7c,0x43,0x07,0xa4]
# CHECK-LE: tlbwe 2, 3, 0 # encoding: [0xa4,0x07,0x43,0x7c]
# CHECK-BE: tlbwehi 2, 3 # encoding: [0x7c,0x43,0x07,0xa4]
# CHECK-LE: tlbwehi 2, 3 # encoding: [0xa4,0x07,0x43,0x7c]
tlbwe %r2, %r3, 0
# CHECK-BE: tlbwe 2, 3, 1 # encoding: [0x7c,0x43,0x0f,0xa4]
# CHECK-LE: tlbwe 2, 3, 1 # encoding: [0xa4,0x0f,0x43,0x7c]
# CHECK-BE: tlbwelo 2, 3 # encoding: [0x7c,0x43,0x0f,0xa4]
# CHECK-LE: tlbwelo 2, 3 # encoding: [0xa4,0x0f,0x43,0x7c]
tlbwe %r2, %r3, 1
# CHECK-BE: tlbwe 2, 3, 0 # encoding: [0x7c,0x43,0x07,0xa4]
# CHECK-LE: tlbwe 2, 3, 0 # encoding: [0xa4,0x07,0x43,0x7c]
# CHECK-BE: tlbwehi 2, 3 # encoding: [0x7c,0x43,0x07,0xa4]
# CHECK-LE: tlbwehi 2, 3 # encoding: [0xa4,0x07,0x43,0x7c]
tlbwehi %r2, %r3
# CHECK-BE: tlbwe 2, 3, 1 # encoding: [0x7c,0x43,0x0f,0xa4]
# CHECK-LE: tlbwe 2, 3, 1 # encoding: [0xa4,0x0f,0x43,0x7c]
# CHECK-BE: tlbwelo 2, 3 # encoding: [0x7c,0x43,0x0f,0xa4]
# CHECK-LE: tlbwelo 2, 3 # encoding: [0xa4,0x0f,0x43,0x7c]
tlbwelo %r2, %r3
# CHECK-BE: tlbsx 2, 3, 1 # encoding: [0x7c,0x43,0x0f,0x24]
@ -43,52 +43,52 @@
# CHECK-LE: tlbsx. 2, 3, 1 # encoding: [0x25,0x0f,0x43,0x7c]
tlbsx. %r2, %r3, %r1
# CHECK-BE: mfspr 2, 1018 # encoding: [0x7c,0x5a,0xfa,0xa6]
# CHECK-LE: mfspr 2, 1018 # encoding: [0xa6,0xfa,0x5a,0x7c]
# CHECK-BE: mfdccr 2 # encoding: [0x7c,0x5a,0xfa,0xa6]
# CHECK-LE: mfdccr 2 # encoding: [0xa6,0xfa,0x5a,0x7c]
mfdccr %r2
# CHECK-BE: mtspr 1018, 2 # encoding: [0x7c,0x5a,0xfb,0xa6]
# CHECK-LE: mtspr 1018, 2 # encoding: [0xa6,0xfb,0x5a,0x7c]
# CHECK-BE: mtdccr 2 # encoding: [0x7c,0x5a,0xfb,0xa6]
# CHECK-LE: mtdccr 2 # encoding: [0xa6,0xfb,0x5a,0x7c]
mtdccr %r2
# CHECK-BE: mfspr 2, 1019 # encoding: [0x7c,0x5b,0xfa,0xa6]
# CHECK-LE: mfspr 2, 1019 # encoding: [0xa6,0xfa,0x5b,0x7c]
# CHECK-BE: mficcr 2 # encoding: [0x7c,0x5b,0xfa,0xa6]
# CHECK-LE: mficcr 2 # encoding: [0xa6,0xfa,0x5b,0x7c]
mficcr %r2
# CHECK-BE: mtspr 1019, 2 # encoding: [0x7c,0x5b,0xfb,0xa6]
# CHECK-LE: mtspr 1019, 2 # encoding: [0xa6,0xfb,0x5b,0x7c]
# CHECK-BE: mticcr 2 # encoding: [0x7c,0x5b,0xfb,0xa6]
# CHECK-LE: mticcr 2 # encoding: [0xa6,0xfb,0x5b,0x7c]
mticcr %r2
# CHECK-BE: mfspr 2, 981 # encoding: [0x7c,0x55,0xf2,0xa6]
# CHECK-LE: mfspr 2, 981 # encoding: [0xa6,0xf2,0x55,0x7c]
# CHECK-BE: mfdear 2 # encoding: [0x7c,0x55,0xf2,0xa6]
# CHECK-LE: mfdear 2 # encoding: [0xa6,0xf2,0x55,0x7c]
mfdear %r2
# CHECK-BE: mtspr 981, 2 # encoding: [0x7c,0x55,0xf3,0xa6]
# CHECK-LE: mtspr 981, 2 # encoding: [0xa6,0xf3,0x55,0x7c]
# CHECK-BE: mtdear 2 # encoding: [0x7c,0x55,0xf3,0xa6]
# CHECK-LE: mtdear 2 # encoding: [0xa6,0xf3,0x55,0x7c]
mtdear %r2
# CHECK-BE: mfspr 2, 980 # encoding: [0x7c,0x54,0xf2,0xa6]
# CHECK-LE: mfspr 2, 980 # encoding: [0xa6,0xf2,0x54,0x7c]
# CHECK-BE: mfesr 2 # encoding: [0x7c,0x54,0xf2,0xa6]
# CHECK-LE: mfesr 2 # encoding: [0xa6,0xf2,0x54,0x7c]
mfesr %r2
# CHECK-BE: mtspr 980, 2 # encoding: [0x7c,0x54,0xf3,0xa6]
# CHECK-LE: mtspr 980, 2 # encoding: [0xa6,0xf3,0x54,0x7c]
# CHECK-BE: mtesr 2 # encoding: [0x7c,0x54,0xf3,0xa6]
# CHECK-LE: mtesr 2 # encoding: [0xa6,0xf3,0x54,0x7c]
mtesr %r2
# CHECK-BE: mfspr 2, 986 # encoding: [0x7c,0x5a,0xf2,0xa6]
# CHECK-LE: mfspr 2, 986 # encoding: [0xa6,0xf2,0x5a,0x7c]
# CHECK-BE: mftcr 2 # encoding: [0x7c,0x5a,0xf2,0xa6]
# CHECK-LE: mftcr 2 # encoding: [0xa6,0xf2,0x5a,0x7c]
mftcr %r2
# CHECK-BE: mtspr 986, 2 # encoding: [0x7c,0x5a,0xf3,0xa6]
# CHECK-LE: mtspr 986, 2 # encoding: [0xa6,0xf3,0x5a,0x7c]
# CHECK-BE: mttcr 2 # encoding: [0x7c,0x5a,0xf3,0xa6]
# CHECK-LE: mttcr 2 # encoding: [0xa6,0xf3,0x5a,0x7c]
mttcr %r2
# CHECK-BE: mfspr 2, 989 # encoding: [0x7c,0x5d,0xf2,0xa6]
# CHECK-LE: mfspr 2, 989 # encoding: [0xa6,0xf2,0x5d,0x7c]
# CHECK-BE: mftblo 2 # encoding: [0x7c,0x5d,0xf2,0xa6]
# CHECK-LE: mftblo 2 # encoding: [0xa6,0xf2,0x5d,0x7c]
mftblo %r2
# CHECK-BE: mtspr 989, 2 # encoding: [0x7c,0x5d,0xf3,0xa6]
# CHECK-LE: mtspr 989, 2 # encoding: [0xa6,0xf3,0x5d,0x7c]
# CHECK-BE: mttblo 2 # encoding: [0x7c,0x5d,0xf3,0xa6]
# CHECK-LE: mttblo 2 # encoding: [0xa6,0xf3,0x5d,0x7c]
mttblo %r2
# CHECK-BE: mfspr 2, 988 # encoding: [0x7c,0x5c,0xf2,0xa6]
# CHECK-LE: mfspr 2, 988 # encoding: [0xa6,0xf2,0x5c,0x7c]
# CHECK-BE: mftbhi 2 # encoding: [0x7c,0x5c,0xf2,0xa6]
# CHECK-LE: mftbhi 2 # encoding: [0xa6,0xf2,0x5c,0x7c]
mftbhi %r2
# CHECK-BE: mtspr 988, 2 # encoding: [0x7c,0x5c,0xf3,0xa6]
# CHECK-LE: mtspr 988, 2 # encoding: [0xa6,0xf3,0x5c,0x7c]
# CHECK-BE: mttbhi 2 # encoding: [0x7c,0x5c,0xf3,0xa6]
# CHECK-LE: mttbhi 2 # encoding: [0xa6,0xf3,0x5c,0x7c]
mttbhi %r2
# CHECK-BE: dccci 5, 6 # encoding: [0x7c,0x05,0x33,0x8c]
@ -104,64 +104,64 @@
# CHECK-LE: iccci 0, 0 # encoding: [0x8c,0x07,0x00,0x7c]
ici 0
# CHECK-BE: mfspr 2, 990 # encoding: [0x7c,0x5e,0xf2,0xa6]
# CHECK-LE: mfspr 2, 990 # encoding: [0xa6,0xf2,0x5e,0x7c]
# CHECK-BE: mfsrr2 2 # encoding: [0x7c,0x5e,0xf2,0xa6]
# CHECK-LE: mfsrr2 2 # encoding: [0xa6,0xf2,0x5e,0x7c]
mfsrr2 2
# CHECK-BE: mtspr 990, 2 # encoding: [0x7c,0x5e,0xf3,0xa6]
# CHECK-LE: mtspr 990, 2 # encoding: [0xa6,0xf3,0x5e,0x7c]
# CHECK-BE: mtsrr2 2 # encoding: [0x7c,0x5e,0xf3,0xa6]
# CHECK-LE: mtsrr2 2 # encoding: [0xa6,0xf3,0x5e,0x7c]
mtsrr2 2
# CHECK-BE: mfspr 2, 991 # encoding: [0x7c,0x5f,0xf2,0xa6]
# CHECK-LE: mfspr 2, 991 # encoding: [0xa6,0xf2,0x5f,0x7c]
# CHECK-BE: mfsrr3 2 # encoding: [0x7c,0x5f,0xf2,0xa6]
# CHECK-LE: mfsrr3 2 # encoding: [0xa6,0xf2,0x5f,0x7c]
mfsrr3 2
# CHECK-BE: mtspr 991, 2 # encoding: [0x7c,0x5f,0xf3,0xa6]
# CHECK-LE: mtspr 991, 2 # encoding: [0xa6,0xf3,0x5f,0x7c]
# CHECK-BE: mtsrr3 2 # encoding: [0x7c,0x5f,0xf3,0xa6]
# CHECK-LE: mtsrr3 2 # encoding: [0xa6,0xf3,0x5f,0x7c]
mtsrr3 2
# CHECK-BE: mfdcr 5, 128 # encoding: [0x7c,0xa0,0x22,0x86]
# CHECK-LE: mfdcr 5, 128 # encoding: [0x86,0x22,0xa0,0x7c]
# CHECK-BE: mfbr0 5 # encoding: [0x7c,0xa0,0x22,0x86]
# CHECK-LE: mfbr0 5 # encoding: [0x86,0x22,0xa0,0x7c]
mfbr0 %r5
# CHECK-BE: mtdcr 128, 5 # encoding: [0x7c,0xa0,0x23,0x86]
# CHECK-LE: mtdcr 128, 5 # encoding: [0x86,0x23,0xa0,0x7c]
# CHECK-BE: mtbr0 5 # encoding: [0x7c,0xa0,0x23,0x86]
# CHECK-LE: mtbr0 5 # encoding: [0x86,0x23,0xa0,0x7c]
mtbr0 %r5
# CHECK-BE: mfdcr 5, 129 # encoding: [0x7c,0xa1,0x22,0x86]
# CHECK-LE: mfdcr 5, 129 # encoding: [0x86,0x22,0xa1,0x7c]
# CHECK-BE: mfbr1 5 # encoding: [0x7c,0xa1,0x22,0x86]
# CHECK-LE: mfbr1 5 # encoding: [0x86,0x22,0xa1,0x7c]
mfbr1 %r5
# CHECK-BE: mtdcr 129, 5 # encoding: [0x7c,0xa1,0x23,0x86]
# CHECK-LE: mtdcr 129, 5 # encoding: [0x86,0x23,0xa1,0x7c]
# CHECK-BE: mtbr1 5 # encoding: [0x7c,0xa1,0x23,0x86]
# CHECK-LE: mtbr1 5 # encoding: [0x86,0x23,0xa1,0x7c]
mtbr1 %r5
# CHECK-BE: mfdcr 5, 130 # encoding: [0x7c,0xa2,0x22,0x86]
# CHECK-LE: mfdcr 5, 130 # encoding: [0x86,0x22,0xa2,0x7c]
# CHECK-BE: mfbr2 5 # encoding: [0x7c,0xa2,0x22,0x86]
# CHECK-LE: mfbr2 5 # encoding: [0x86,0x22,0xa2,0x7c]
mfbr2 %r5
# CHECK-BE: mtdcr 130, 5 # encoding: [0x7c,0xa2,0x23,0x86]
# CHECK-LE: mtdcr 130, 5 # encoding: [0x86,0x23,0xa2,0x7c]
# CHECK-BE: mtbr2 5 # encoding: [0x7c,0xa2,0x23,0x86]
# CHECK-LE: mtbr2 5 # encoding: [0x86,0x23,0xa2,0x7c]
mtbr2 %r5
# CHECK-BE: mfdcr 5, 131 # encoding: [0x7c,0xa3,0x22,0x86]
# CHECK-LE: mfdcr 5, 131 # encoding: [0x86,0x22,0xa3,0x7c]
# CHECK-BE: mfbr3 5 # encoding: [0x7c,0xa3,0x22,0x86]
# CHECK-LE: mfbr3 5 # encoding: [0x86,0x22,0xa3,0x7c]
mfbr3 %r5
# CHECK-BE: mtdcr 131, 5 # encoding: [0x7c,0xa3,0x23,0x86]
# CHECK-LE: mtdcr 131, 5 # encoding: [0x86,0x23,0xa3,0x7c]
# CHECK-BE: mtbr3 5 # encoding: [0x7c,0xa3,0x23,0x86]
# CHECK-LE: mtbr3 5 # encoding: [0x86,0x23,0xa3,0x7c]
mtbr3 %r5
# CHECK-BE: mfdcr 5, 132 # encoding: [0x7c,0xa4,0x22,0x86]
# CHECK-LE: mfdcr 5, 132 # encoding: [0x86,0x22,0xa4,0x7c]
# CHECK-BE: mfbr4 5 # encoding: [0x7c,0xa4,0x22,0x86]
# CHECK-LE: mfbr4 5 # encoding: [0x86,0x22,0xa4,0x7c]
mfbr4 %r5
# CHECK-BE: mtdcr 132, 5 # encoding: [0x7c,0xa4,0x23,0x86]
# CHECK-LE: mtdcr 132, 5 # encoding: [0x86,0x23,0xa4,0x7c]
# CHECK-BE: mtbr4 5 # encoding: [0x7c,0xa4,0x23,0x86]
# CHECK-LE: mtbr4 5 # encoding: [0x86,0x23,0xa4,0x7c]
mtbr4 %r5
# CHECK-BE: mfdcr 5, 133 # encoding: [0x7c,0xa5,0x22,0x86]
# CHECK-LE: mfdcr 5, 133 # encoding: [0x86,0x22,0xa5,0x7c]
# CHECK-BE: mfbr5 5 # encoding: [0x7c,0xa5,0x22,0x86]
# CHECK-LE: mfbr5 5 # encoding: [0x86,0x22,0xa5,0x7c]
mfbr5 %r5
# CHECK-BE: mtdcr 133, 5 # encoding: [0x7c,0xa5,0x23,0x86]
# CHECK-LE: mtdcr 133, 5 # encoding: [0x86,0x23,0xa5,0x7c]
# CHECK-BE: mtbr5 5 # encoding: [0x7c,0xa5,0x23,0x86]
# CHECK-LE: mtbr5 5 # encoding: [0x86,0x23,0xa5,0x7c]
mtbr5 %r5
# CHECK-BE: mfdcr 5, 134 # encoding: [0x7c,0xa6,0x22,0x86]
# CHECK-LE: mfdcr 5, 134 # encoding: [0x86,0x22,0xa6,0x7c]
# CHECK-BE: mfbr6 5 # encoding: [0x7c,0xa6,0x22,0x86]
# CHECK-LE: mfbr6 5 # encoding: [0x86,0x22,0xa6,0x7c]
mfbr6 %r5
# CHECK-BE: mtdcr 134, 5 # encoding: [0x7c,0xa6,0x23,0x86]
# CHECK-LE: mtdcr 134, 5 # encoding: [0x86,0x23,0xa6,0x7c]
# CHECK-BE: mtbr6 5 # encoding: [0x7c,0xa6,0x23,0x86]
# CHECK-LE: mtbr6 5 # encoding: [0x86,0x23,0xa6,0x7c]
mtbr6 %r5
# CHECK-BE: mfdcr 5, 135 # encoding: [0x7c,0xa7,0x22,0x86]
# CHECK-LE: mfdcr 5, 135 # encoding: [0x86,0x22,0xa7,0x7c]
# CHECK-BE: mfbr7 5 # encoding: [0x7c,0xa7,0x22,0x86]
# CHECK-LE: mfbr7 5 # encoding: [0x86,0x22,0xa7,0x7c]
mfbr7 %r5
# CHECK-BE: mtdcr 135, 5 # encoding: [0x7c,0xa7,0x23,0x86]
# CHECK-LE: mtdcr 135, 5 # encoding: [0x86,0x23,0xa7,0x7c]
# CHECK-BE: mtbr7 5 # encoding: [0x7c,0xa7,0x23,0x86]
# CHECK-LE: mtbr7 5 # encoding: [0x86,0x23,0xa7,0x7c]
mtbr7 %r5

128
llvm/test/MC/PowerPC/ppc64-encoding-6xx.s
View File

@ -3,102 +3,102 @@
# Instructions specific to the PowerPC 6xx family:
# CHECK-BE: mfspr 12, 528 # encoding: [0x7d,0x90,0x82,0xa6]
# CHECK-LE: mfspr 12, 528 # encoding: [0xa6,0x82,0x90,0x7d]
# CHECK-BE: mfibatu 12, 0 # encoding: [0x7d,0x90,0x82,0xa6]
# CHECK-LE: mfibatu 12, 0 # encoding: [0xa6,0x82,0x90,0x7d]
mfibatu %r12, 0
# CHECK-BE: mfspr 12, 529 # encoding: [0x7d,0x91,0x82,0xa6]
# CHECK-LE: mfspr 12, 529 # encoding: [0xa6,0x82,0x91,0x7d]
# CHECK-BE: mfibatl 12, 0 # encoding: [0x7d,0x91,0x82,0xa6]
# CHECK-LE: mfibatl 12, 0 # encoding: [0xa6,0x82,0x91,0x7d]
mfibatl %r12, 0
# CHECK-BE: mfspr 12, 530 # encoding: [0x7d,0x92,0x82,0xa6]
# CHECK-LE: mfspr 12, 530 # encoding: [0xa6,0x82,0x92,0x7d]
# CHECK-BE: mfibatu 12, 1 # encoding: [0x7d,0x92,0x82,0xa6]
# CHECK-LE: mfibatu 12, 1 # encoding: [0xa6,0x82,0x92,0x7d]
mfibatu %r12, 1
# CHECK-BE: mfspr 12, 531 # encoding: [0x7d,0x93,0x82,0xa6]
# CHECK-LE: mfspr 12, 531 # encoding: [0xa6,0x82,0x93,0x7d]
# CHECK-BE: mfibatl 12, 1 # encoding: [0x7d,0x93,0x82,0xa6]
# CHECK-LE: mfibatl 12, 1 # encoding: [0xa6,0x82,0x93,0x7d]
mfibatl %r12, 1
# CHECK-BE: mfspr 12, 532 # encoding: [0x7d,0x94,0x82,0xa6]
# CHECK-LE: mfspr 12, 532 # encoding: [0xa6,0x82,0x94,0x7d]
# CHECK-BE: mfibatu 12, 2 # encoding: [0x7d,0x94,0x82,0xa6]
# CHECK-LE: mfibatu 12, 2 # encoding: [0xa6,0x82,0x94,0x7d]
mfibatu %r12, 2
# CHECK-BE: mfspr 12, 533 # encoding: [0x7d,0x95,0x82,0xa6]
# CHECK-LE: mfspr 12, 533 # encoding: [0xa6,0x82,0x95,0x7d]
# CHECK-BE: mfibatl 12, 2 # encoding: [0x7d,0x95,0x82,0xa6]
# CHECK-LE: mfibatl 12, 2 # encoding: [0xa6,0x82,0x95,0x7d]
mfibatl %r12, 2
# CHECK-BE: mfspr 12, 534 # encoding: [0x7d,0x96,0x82,0xa6]
# CHECK-LE: mfspr 12, 534 # encoding: [0xa6,0x82,0x96,0x7d]
# CHECK-BE: mfibatu 12, 3 # encoding: [0x7d,0x96,0x82,0xa6]
# CHECK-LE: mfibatu 12, 3 # encoding: [0xa6,0x82,0x96,0x7d]
mfibatu %r12, 3
# CHECK-BE: mfspr 12, 535 # encoding: [0x7d,0x97,0x82,0xa6]
# CHECK-LE: mfspr 12, 535 # encoding: [0xa6,0x82,0x97,0x7d]
# CHECK-BE: mfibatl 12, 3 # encoding: [0x7d,0x97,0x82,0xa6]
# CHECK-LE: mfibatl 12, 3 # encoding: [0xa6,0x82,0x97,0x7d]
mfibatl %r12, 3
# CHECK-BE: mtspr 528, 12 # encoding: [0x7d,0x90,0x83,0xa6]
# CHECK-LE: mtspr 528, 12 # encoding: [0xa6,0x83,0x90,0x7d]
# CHECK-BE: mtibatu 0, 12 # encoding: [0x7d,0x90,0x83,0xa6]
# CHECK-LE: mtibatu 0, 12 # encoding: [0xa6,0x83,0x90,0x7d]
mtibatu 0, %r12
# CHECK-BE: mtspr 529, 12 # encoding: [0x7d,0x91,0x83,0xa6]
# CHECK-LE: mtspr 529, 12 # encoding: [0xa6,0x83,0x91,0x7d]
# CHECK-BE: mtibatl 0, 12 # encoding: [0x7d,0x91,0x83,0xa6]
# CHECK-LE: mtibatl 0, 12 # encoding: [0xa6,0x83,0x91,0x7d]
mtibatl 0, %r12
# CHECK-BE: mtspr 530, 12 # encoding: [0x7d,0x92,0x83,0xa6]
# CHECK-LE: mtspr 530, 12 # encoding: [0xa6,0x83,0x92,0x7d]
# CHECK-BE: mtibatu 1, 12 # encoding: [0x7d,0x92,0x83,0xa6]
# CHECK-LE: mtibatu 1, 12 # encoding: [0xa6,0x83,0x92,0x7d]
mtibatu 1, %r12
# CHECK-BE: mtspr 531, 12 # encoding: [0x7d,0x93,0x83,0xa6]
# CHECK-LE: mtspr 531, 12 # encoding: [0xa6,0x83,0x93,0x7d]
# CHECK-BE: mtibatl 1, 12 # encoding: [0x7d,0x93,0x83,0xa6]
# CHECK-LE: mtibatl 1, 12 # encoding: [0xa6,0x83,0x93,0x7d]
mtibatl 1, %r12
# CHECK-BE: mtspr 532, 12 # encoding: [0x7d,0x94,0x83,0xa6]
# CHECK-LE: mtspr 532, 12 # encoding: [0xa6,0x83,0x94,0x7d]
# CHECK-BE: mtibatu 2, 12 # encoding: [0x7d,0x94,0x83,0xa6]
# CHECK-LE: mtibatu 2, 12 # encoding: [0xa6,0x83,0x94,0x7d]
mtibatu 2, %r12
# CHECK-BE: mtspr 533, 12 # encoding: [0x7d,0x95,0x83,0xa6]
# CHECK-LE: mtspr 533, 12 # encoding: [0xa6,0x83,0x95,0x7d]
# CHECK-BE: mtibatl 2, 12 # encoding: [0x7d,0x95,0x83,0xa6]
# CHECK-LE: mtibatl 2, 12 # encoding: [0xa6,0x83,0x95,0x7d]
mtibatl 2, %r12
# CHECK-BE: mtspr 534, 12 # encoding: [0x7d,0x96,0x83,0xa6]
# CHECK-LE: mtspr 534, 12 # encoding: [0xa6,0x83,0x96,0x7d]
# CHECK-BE: mtibatu 3, 12 # encoding: [0x7d,0x96,0x83,0xa6]
# CHECK-LE: mtibatu 3, 12 # encoding: [0xa6,0x83,0x96,0x7d]
mtibatu 3, %r12
# CHECK-BE: mtspr 535, 12 # encoding: [0x7d,0x97,0x83,0xa6]
# CHECK-LE: mtspr 535, 12 # encoding: [0xa6,0x83,0x97,0x7d]
# CHECK-BE: mtibatl 3, 12 # encoding: [0x7d,0x97,0x83,0xa6]
# CHECK-LE: mtibatl 3, 12 # encoding: [0xa6,0x83,0x97,0x7d]
mtibatl 3, %r12
# CHECK-BE: mfspr 12, 536 # encoding: [0x7d,0x98,0x82,0xa6]
# CHECK-LE: mfspr 12, 536 # encoding: [0xa6,0x82,0x98,0x7d]
# CHECK-BE: mfdbatu 12, 0 # encoding: [0x7d,0x98,0x82,0xa6]
# CHECK-LE: mfdbatu 12, 0 # encoding: [0xa6,0x82,0x98,0x7d]
mfdbatu %r12, 0
# CHECK-BE: mfspr 12, 537 # encoding: [0x7d,0x99,0x82,0xa6]
# CHECK-LE: mfspr 12, 537 # encoding: [0xa6,0x82,0x99,0x7d]
# CHECK-BE: mfdbatl 12, 0 # encoding: [0x7d,0x99,0x82,0xa6]
# CHECK-LE: mfdbatl 12, 0 # encoding: [0xa6,0x82,0x99,0x7d]
mfdbatl %r12, 0
# CHECK-BE: mfspr 12, 538 # encoding: [0x7d,0x9a,0x82,0xa6]
# CHECK-LE: mfspr 12, 538 # encoding: [0xa6,0x82,0x9a,0x7d]
# CHECK-BE: mfdbatu 12, 1 # encoding: [0x7d,0x9a,0x82,0xa6]
# CHECK-LE: mfdbatu 12, 1 # encoding: [0xa6,0x82,0x9a,0x7d]
mfdbatu %r12, 1
# CHECK-BE: mfspr 12, 539 # encoding: [0x7d,0x9b,0x82,0xa6]
# CHECK-LE: mfspr 12, 539 # encoding: [0xa6,0x82,0x9b,0x7d]
# CHECK-BE: mfdbatl 12, 1 # encoding: [0x7d,0x9b,0x82,0xa6]
# CHECK-LE: mfdbatl 12, 1 # encoding: [0xa6,0x82,0x9b,0x7d]
mfdbatl %r12, 1
# CHECK-BE: mfspr 12, 540 # encoding: [0x7d,0x9c,0x82,0xa6]
# CHECK-LE: mfspr 12, 540 # encoding: [0xa6,0x82,0x9c,0x7d]
# CHECK-BE: mfdbatu 12, 2 # encoding: [0x7d,0x9c,0x82,0xa6]
# CHECK-LE: mfdbatu 12, 2 # encoding: [0xa6,0x82,0x9c,0x7d]
mfdbatu %r12, 2
# CHECK-BE: mfspr 12, 541 # encoding: [0x7d,0x9d,0x82,0xa6]
# CHECK-LE: mfspr 12, 541 # encoding: [0xa6,0x82,0x9d,0x7d]
# CHECK-BE: mfdbatl 12, 2 # encoding: [0x7d,0x9d,0x82,0xa6]
# CHECK-LE: mfdbatl 12, 2 # encoding: [0xa6,0x82,0x9d,0x7d]
mfdbatl %r12, 2
# CHECK-BE: mfspr 12, 542 # encoding: [0x7d,0x9e,0x82,0xa6]
# CHECK-LE: mfspr 12, 542 # encoding: [0xa6,0x82,0x9e,0x7d]
# CHECK-BE: mfdbatu 12, 3 # encoding: [0x7d,0x9e,0x82,0xa6]
# CHECK-LE: mfdbatu 12, 3 # encoding: [0xa6,0x82,0x9e,0x7d]
mfdbatu %r12, 3
# CHECK-BE: mfspr 12, 543 # encoding: [0x7d,0x9f,0x82,0xa6]
# CHECK-LE: mfspr 12, 543 # encoding: [0xa6,0x82,0x9f,0x7d]
# CHECK-BE: mfdbatl 12, 3 # encoding: [0x7d,0x9f,0x82,0xa6]
# CHECK-LE: mfdbatl 12, 3 # encoding: [0xa6,0x82,0x9f,0x7d]
mfdbatl %r12, 3
# CHECK-BE: mtspr 536, 12 # encoding: [0x7d,0x98,0x83,0xa6]
# CHECK-LE: mtspr 536, 12 # encoding: [0xa6,0x83,0x98,0x7d]
# CHECK-BE: mtdbatu 0, 12 # encoding: [0x7d,0x98,0x83,0xa6]
# CHECK-LE: mtdbatu 0, 12 # encoding: [0xa6,0x83,0x98,0x7d]
mtdbatu 0, %r12
# CHECK-BE: mtspr 537, 12 # encoding: [0x7d,0x99,0x83,0xa6]
# CHECK-LE: mtspr 537, 12 # encoding: [0xa6,0x83,0x99,0x7d]
# CHECK-BE: mtdbatl 0, 12 # encoding: [0x7d,0x99,0x83,0xa6]
# CHECK-LE: mtdbatl 0, 12 # encoding: [0xa6,0x83,0x99,0x7d]
mtdbatl 0, %r12
# CHECK-BE: mtspr 538, 12 # encoding: [0x7d,0x9a,0x83,0xa6]
# CHECK-LE: mtspr 538, 12 # encoding: [0xa6,0x83,0x9a,0x7d]
# CHECK-BE: mtdbatu 1, 12 # encoding: [0x7d,0x9a,0x83,0xa6]
# CHECK-LE: mtdbatu 1, 12 # encoding: [0xa6,0x83,0x9a,0x7d]
mtdbatu 1, %r12
# CHECK-BE: mtspr 539, 12 # encoding: [0x7d,0x9b,0x83,0xa6]
# CHECK-LE: mtspr 539, 12 # encoding: [0xa6,0x83,0x9b,0x7d]
# CHECK-BE: mtdbatl 1, 12 # encoding: [0x7d,0x9b,0x83,0xa6]
# CHECK-LE: mtdbatl 1, 12 # encoding: [0xa6,0x83,0x9b,0x7d]
mtdbatl 1, %r12
# CHECK-BE: mtspr 540, 12 # encoding: [0x7d,0x9c,0x83,0xa6]
# CHECK-LE: mtspr 540, 12 # encoding: [0xa6,0x83,0x9c,0x7d]
# CHECK-BE: mtdbatu 2, 12 # encoding: [0x7d,0x9c,0x83,0xa6]
# CHECK-LE: mtdbatu 2, 12 # encoding: [0xa6,0x83,0x9c,0x7d]
mtdbatu 2, %r12
# CHECK-BE: mtspr 541, 12 # encoding: [0x7d,0x9d,0x83,0xa6]
# CHECK-LE: mtspr 541, 12 # encoding: [0xa6,0x83,0x9d,0x7d]
# CHECK-BE: mtdbatl 2, 12 # encoding: [0x7d,0x9d,0x83,0xa6]
# CHECK-LE: mtdbatl 2, 12 # encoding: [0xa6,0x83,0x9d,0x7d]
mtdbatl 2, %r12
# CHECK-BE: mtspr 542, 12 # encoding: [0x7d,0x9e,0x83,0xa6]
# CHECK-LE: mtspr 542, 12 # encoding: [0xa6,0x83,0x9e,0x7d]
# CHECK-BE: mtdbatu 3, 12 # encoding: [0x7d,0x9e,0x83,0xa6]
# CHECK-LE: mtdbatu 3, 12 # encoding: [0xa6,0x83,0x9e,0x7d]
mtdbatu 3, %r12
# CHECK-BE: mtspr 543, 12 # encoding: [0x7d,0x9f,0x83,0xa6]
# CHECK-LE: mtspr 543, 12 # encoding: [0xa6,0x83,0x9f,0x7d]
# CHECK-BE: mtdbatl 3, 12 # encoding: [0x7d,0x9f,0x83,0xa6]
# CHECK-LE: mtdbatl 3, 12 # encoding: [0xa6,0x83,0x9f,0x7d]
mtdbatl 3, %r12
# CHECK-BE: tlbld 4 # encoding: [0x7c,0x00,0x27,0xa4]

42
llvm/test/MC/PowerPC/ppc64-encoding-bookII.s
View File

@ -43,19 +43,19 @@
# CHECK-LE: stdcx. 2, 3, 4 # encoding: [0xad,0x21,0x43,0x7c]
stdcx. 2, 3, 4
# CHECK-BE: sync 2 # encoding: [0x7c,0x40,0x04,0xac]
# CHECK-LE: sync 2 # encoding: [0xac,0x04,0x40,0x7c]
# CHECK-BE: ptesync # encoding: [0x7c,0x40,0x04,0xac]
# CHECK-LE: ptesync # encoding: [0xac,0x04,0x40,0x7c]
sync 2
# CHECK-BE: eieio # encoding: [0x7c,0x00,0x06,0xac]
# CHECK-LE: eieio # encoding: [0xac,0x06,0x00,0x7c]
eieio
# CHECK-BE: wait 2 # encoding: [0x7c,0x40,0x00,0x7c]
# CHECK-LE: wait 2 # encoding: [0x7c,0x00,0x40,0x7c]
# CHECK-BE: waitimpl # encoding: [0x7c,0x40,0x00,0x7c]
# CHECK-LE: waitimpl # encoding: [0x7c,0x00,0x40,0x7c]
wait 2
# CHECK-BE: mbar 1 # encoding: [0x7c,0x20,0x06,0xac]
# CHECK-LE: mbar 1 # encoding: [0xac,0x06,0x20,0x7c]
mbar 1
# CHECK-BE: mbar 0
# CHECK-BE: mbar # encoding: [0x7c,0x00,0x06,0xac]
mbar
# Extended mnemonics
@ -103,21 +103,21 @@
# CHECK-BE: sync 0 # encoding: [0x7c,0x00,0x04,0xac]
# CHECK-LE: sync 0 # encoding: [0xac,0x04,0x00,0x7c]
msync
# CHECK-BE: sync 1 # encoding: [0x7c,0x20,0x04,0xac]
# CHECK-LE: sync 1 # encoding: [0xac,0x04,0x20,0x7c]
# CHECK-BE: lwsync # encoding: [0x7c,0x20,0x04,0xac]
# CHECK-LE: lwsync # encoding: [0xac,0x04,0x20,0x7c]
lwsync
# CHECK-BE: sync 2 # encoding: [0x7c,0x40,0x04,0xac]
# CHECK-LE: sync 2 # encoding: [0xac,0x04,0x40,0x7c]
# CHECK-BE: ptesync # encoding: [0x7c,0x40,0x04,0xac]
# CHECK-LE: ptesync # encoding: [0xac,0x04,0x40,0x7c]
ptesync
# CHECK-BE: wait 0 # encoding: [0x7c,0x00,0x00,0x7c]
# CHECK-LE: wait 0 # encoding: [0x7c,0x00,0x00,0x7c]
# CHECK-BE: wait # encoding: [0x7c,0x00,0x00,0x7c]
# CHECK-LE: wait # encoding: [0x7c,0x00,0x00,0x7c]
wait
# CHECK-BE: wait 1 # encoding: [0x7c,0x20,0x00,0x7c]
# CHECK-LE: wait 1 # encoding: [0x7c,0x00,0x20,0x7c]
# CHECK-BE: waitrsv # encoding: [0x7c,0x20,0x00,0x7c]
# CHECK-LE: waitrsv # encoding: [0x7c,0x00,0x20,0x7c]
waitrsv
# CHECK-BE: wait 2 # encoding: [0x7c,0x40,0x00,0x7c]
# CHECK-LE: wait 2 # encoding: [0x7c,0x00,0x40,0x7c]
# CHECK-BE: waitimpl # encoding: [0x7c,0x40,0x00,0x7c]
# CHECK-LE: waitimpl # encoding: [0x7c,0x00,0x40,0x7c]
waitimpl
# Time base instructions
@ -131,13 +131,13 @@
# CHECK-BE: mftb 2, 268 # encoding: [0x7c,0x4c,0x42,0xe6]
# CHECK-LE: mftb 2, 268 # encoding: [0xe6,0x42,0x4c,0x7c]
mftbl 2
# CHECK-BE: mftb 2, 269 # encoding: [0x7c,0x4d,0x42,0xe6]
# CHECK-LE: mftb 2, 269 # encoding: [0xe6,0x42,0x4d,0x7c]
# CHECK-BE: mftbu 2 # encoding: [0x7c,0x4d,0x42,0xe6]
# CHECK-LE: mftbu 2 # encoding: [0xe6,0x42,0x4d,0x7c]
mftbu 2
# CHECK-BE: mtspr 284, 3 # encoding: [0x7c,0x7c,0x43,0xa6]
# CHECK-LE: mtspr 284, 3 # encoding: [0xa6,0x43,0x7c,0x7c]
# CHECK-BE: mttbl 3 # encoding: [0x7c,0x7c,0x43,0xa6]
# CHECK-LE: mttbl 3 # encoding: [0xa6,0x43,0x7c,0x7c]
mttbl 3
# CHECK-BE: mtspr 285, 3 # encoding: [0x7c,0x7d,0x43,0xa6]
# CHECK-LE: mtspr 285, 3 # encoding: [0xa6,0x43,0x7d,0x7c]
# CHECK-BE: mttbu 3 # encoding: [0x7c,0x7d,0x43,0xa6]
# CHECK-LE: mttbu 3 # encoding: [0xa6,0x43,0x7d,0x7c]
mttbu 3

20
llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s
View File

@ -1,8 +1,8 @@
# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s
# CHECK-BE: mtmsr 4, 0 # encoding: [0x7c,0x80,0x01,0x24]
# CHECK-LE: mtmsr 4, 0 # encoding: [0x24,0x01,0x80,0x7c]
# CHECK-BE: mtmsr 4 # encoding: [0x7c,0x80,0x01,0x24]
# CHECK-LE: mtmsr 4 # encoding: [0x24,0x01,0x80,0x7c]
mtmsr %r4
# CHECK-BE: mtmsr 4, 1 # encoding: [0x7c,0x81,0x01,0x24]
@ -13,8 +13,8 @@
# CHECK-LE: mfmsr 4 # encoding: [0xa6,0x00,0x80,0x7c]
mfmsr %r4
# CHECK-BE: mtmsrd 4, 0 # encoding: [0x7c,0x80,0x01,0x64]
# CHECK-LE: mtmsrd 4, 0 # encoding: [0x64,0x01,0x80,0x7c]
# CHECK-BE: mtmsrd 4 # encoding: [0x7c,0x80,0x01,0x64]
# CHECK-LE: mtmsrd 4 # encoding: [0x64,0x01,0x80,0x7c]
mtmsrd %r4
# CHECK-BE: mtmsrd 4, 1 # encoding: [0x7c,0x81,0x01,0x64]
@ -94,8 +94,8 @@
# CHECK-LE: mtspr 22, 4 # encoding: [0xa6,0x03,0x96,0x7c]
mtdec %r4
# CHECK-BE: mfspr 4, 287 # encoding: [0x7c,0x9f,0x42,0xa6]
# CHECK-LE: mfspr 4, 287 # encoding: [0xa6,0x42,0x9f,0x7c]
# CHECK-BE: mfpvr 4 # encoding: [0x7c,0x9f,0x42,0xa6]
# CHECK-LE: mfpvr 4 # encoding: [0xa6,0x42,0x9f,0x7c]
mfpvr %r4
# CHECK-BE: mfspr 4, 25 # encoding: [0x7c,0x99,0x02,0xa6]
@ -146,12 +146,12 @@
# CHECK-LE: tlbiel 4 # encoding: [0x24,0x22,0x00,0x7c]
tlbiel %r4
# CHECK-BE: tlbie 4,0 # encoding: [0x7c,0x00,0x22,0x64]
# CHECK-LE: tlbie 4,0 # encoding: [0x64,0x22,0x00,0x7c]
# CHECK-BE: tlbie 4 # encoding: [0x7c,0x00,0x22,0x64]
# CHECK-LE: tlbie 4 # encoding: [0x64,0x22,0x00,0x7c]
tlbie %r4, 0
# CHECK-BE: tlbie 4,0 # encoding: [0x7c,0x00,0x22,0x64]
# CHECK-LE: tlbie 4,0 # encoding: [0x64,0x22,0x00,0x7c]
# CHECK-BE: tlbie 4 # encoding: [0x7c,0x00,0x22,0x64]
# CHECK-LE: tlbie 4 # encoding: [0x64,0x22,0x00,0x7c]
tlbie %r4
# CHECK-BE: rfi # encoding: [0x4c,0x00,0x00,0x64]

780
llvm/test/MC/PowerPC/ppc64-encoding-ext.s
View File

File diff suppressed because it is too large Load Diff

16
llvm/test/MC/PowerPC/ppc64-encoding-fp.s
View File

@ -371,11 +371,11 @@
# CHECK-BE: mtfsfi. 5, 2, 1 # encoding: [0xfe,0x81,0x21,0x0d]
# CHECK-LE: mtfsfi. 5, 2, 1 # encoding: [0x0d,0x21,0x81,0xfe]
mtfsfi. 5, 2, 1
# CHECK-BE: mtfsfi 6, 2, 0 # encoding: [0xff,0x00,0x21,0x0c]
# CHECK-LE: mtfsfi 6, 2, 0 # encoding: [0x0c,0x21,0x00,0xff]
# CHECK-BE: mtfsfi 6, 2 # encoding: [0xff,0x00,0x21,0x0c]
# CHECK-LE: mtfsfi 6, 2 # encoding: [0x0c,0x21,0x00,0xff]
mtfsfi 6, 2
# CHECK-BE: mtfsfi. 6, 2, 0 # encoding: [0xff,0x00,0x21,0x0d]
# CHECK-LE: mtfsfi. 6, 2, 0 # encoding: [0x0d,0x21,0x00,0xff]
# CHECK-BE: mtfsfi. 6, 2 # encoding: [0xff,0x00,0x21,0x0d]
# CHECK-LE: mtfsfi. 6, 2 # encoding: [0x0d,0x21,0x00,0xff]
mtfsfi. 6, 2
# CHECK-BE: mtfsf 127, 8, 1, 1 # encoding: [0xfe,0xff,0x45,0x8e]
# CHECK-LE: mtfsf 127, 8, 1, 1 # encoding: [0x8e,0x45,0xff,0xfe]
@ -383,11 +383,11 @@
# CHECK-BE: mtfsf. 125, 8, 1, 1 # encoding: [0xfe,0xfb,0x45,0x8f]
# CHECK-LE: mtfsf. 125, 8, 1, 1 # encoding: [0x8f,0x45,0xfb,0xfe]
mtfsf. 125, 8, 1, 1
# CHECK-BE: mtfsf 127, 6, 0, 0 # encoding: [0xfc,0xfe,0x35,0x8e]
# CHECK-LE: mtfsf 127, 6, 0, 0 # encoding: [0x8e,0x35,0xfe,0xfc]
# CHECK-BE: mtfsf 127, 6 # encoding: [0xfc,0xfe,0x35,0x8e]
# CHECK-LE: mtfsf 127, 6 # encoding: [0x8e,0x35,0xfe,0xfc]
mtfsf 127, 6
# CHECK-BE: mtfsf. 125, 6, 0, 0 # encoding: [0xfc,0xfa,0x35,0x8f]
# CHECK-LE: mtfsf. 125, 6, 0, 0 # encoding: [0x8f,0x35,0xfa,0xfc]
# CHECK-BE: mtfsf. 125, 6 # encoding: [0xfc,0xfa,0x35,0x8f]
# CHECK-LE: mtfsf. 125, 6 # encoding: [0x8f,0x35,0xfa,0xfc]
mtfsf. 125, 6
# CHECK-BE: mtfsb0 31 # encoding: [0xff,0xe0,0x00,0x8c]
# CHECK-LE: mtfsb0 31 # encoding: [0x8c,0x00,0xe0,0xff]

68
llvm/test/MC/PowerPC/ppc64-encoding.s
View File

@ -27,23 +27,23 @@
# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs
bla target
# CHECK-BE: bc 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA00]
# CHECK-LE: bc 4, 10, target # encoding: [0bAAAAAA00,A,0x8a,0x40]
# CHECK-BE: bf 10, target # encoding: [0x40,0x8a,A,0bAAAAAA00]
# CHECK-LE: bf 10, target # encoding: [0bAAAAAA00,A,0x8a,0x40]
# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bc 4, 10, target
# CHECK-BE: bca 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA10]
# CHECK-LE: bca 4, 10, target # encoding: [0bAAAAAA10,A,0x8a,0x40]
# CHECK-BE: bfa 10, target # encoding: [0x40,0x8a,A,0bAAAAAA10]
# CHECK-LE: bfa 10, target # encoding: [0bAAAAAA10,A,0x8a,0x40]
# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bca 4, 10, target
# CHECK-BE: bcl 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA01]
# CHECK-LE: bcl 4, 10, target # encoding: [0bAAAAAA01,A,0x8a,0x40]
# CHECK-BE: bfl 10, target # encoding: [0x40,0x8a,A,0bAAAAAA01]
# CHECK-LE: bfl 10, target # encoding: [0bAAAAAA01,A,0x8a,0x40]
# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bcl 4, 10, target
# CHECK-BE: bcla 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA11]
# CHECK-LE: bcla 4, 10, target # encoding: [0bAAAAAA11,A,0x8a,0x40]
# CHECK-BE: bfla 10, target # encoding: [0x40,0x8a,A,0bAAAAAA11]
# CHECK-LE: bfla 10, target # encoding: [0bAAAAAA11,A,0x8a,0x40]
# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bcla 4, 10, target
@ -51,26 +51,26 @@
# CHECK-BE: bclr 4, 10, 3 # encoding: [0x4c,0x8a,0x18,0x20]
# CHECK-LE: bclr 4, 10, 3 # encoding: [0x20,0x18,0x8a,0x4c]
bclr 4, 10, 3
# CHECK-BE: bclr 4, 10, 0 # encoding: [0x4c,0x8a,0x00,0x20]
# CHECK-LE: bclr 4, 10, 0 # encoding: [0x20,0x00,0x8a,0x4c]
# CHECK-BE: bclr 4, 10 # encoding: [0x4c,0x8a,0x00,0x20]
# CHECK-LE: bclr 4, 10 # encoding: [0x20,0x00,0x8a,0x4c]
bclr 4, 10
# CHECK-BE: bclrl 4, 10, 3 # encoding: [0x4c,0x8a,0x18,0x21]
# CHECK-LE: bclrl 4, 10, 3 # encoding: [0x21,0x18,0x8a,0x4c]
bclrl 4, 10, 3
# CHECK-BE: bclrl 4, 10, 0 # encoding: [0x4c,0x8a,0x00,0x21]
# CHECK-LE: bclrl 4, 10, 0 # encoding: [0x21,0x00,0x8a,0x4c]
# CHECK-BE: bclrl 4, 10 # encoding: [0x4c,0x8a,0x00,0x21]
# CHECK-LE: bclrl 4, 10 # encoding: [0x21,0x00,0x8a,0x4c]
bclrl 4, 10
# CHECK-BE: bcctr 4, 10, 3 # encoding: [0x4c,0x8a,0x1c,0x20]
# CHECK-LE: bcctr 4, 10, 3 # encoding: [0x20,0x1c,0x8a,0x4c]
bcctr 4, 10, 3
# CHECK-BE: bcctr 4, 10, 0 # encoding: [0x4c,0x8a,0x04,0x20]
# CHECK-LE: bcctr 4, 10, 0 # encoding: [0x20,0x04,0x8a,0x4c]
# CHECK-BE: bcctr 4, 10 # encoding: [0x4c,0x8a,0x04,0x20]
# CHECK-LE: bcctr 4, 10 # encoding: [0x20,0x04,0x8a,0x4c]
bcctr 4, 10
# CHECK-BE: bcctrl 4, 10, 3 # encoding: [0x4c,0x8a,0x1c,0x21]
# CHECK-LE: bcctrl 4, 10, 3 # encoding: [0x21,0x1c,0x8a,0x4c]
bcctrl 4, 10, 3
# CHECK-BE: bcctrl 4, 10, 0 # encoding: [0x4c,0x8a,0x04,0x21]
# CHECK-LE: bcctrl 4, 10, 0 # encoding: [0x21,0x04,0x8a,0x4c]
# CHECK-BE: bcctrl 4, 10 # encoding: [0x4c,0x8a,0x04,0x21]
# CHECK-LE: bcctrl 4, 10 # encoding: [0x21,0x04,0x8a,0x4c]
bcctrl 4, 10
# Condition register instructions
@ -108,8 +108,8 @@
# CHECK-BE: sc 1 # encoding: [0x44,0x00,0x00,0x22]
# CHECK-LE: sc 1 # encoding: [0x22,0x00,0x00,0x44]
sc 1
# CHECK-BE: sc 0 # encoding: [0x44,0x00,0x00,0x02]
# CHECK-LE: sc 0 # encoding: [0x02,0x00,0x00,0x44]
# CHECK-BE: sc # encoding: [0x44,0x00,0x00,0x02]
# CHECK-LE: sc # encoding: [0x02,0x00,0x00,0x44]
sc
# Fixed-point facility
@ -521,17 +521,17 @@
# Fixed-point trap instructions
# CHECK-BE: twi 2, 3, 4 # encoding: [0x0c,0x43,0x00,0x04]
# CHECK-LE: twi 2, 3, 4 # encoding: [0x04,0x00,0x43,0x0c]
# CHECK-BE: twllti 3, 4 # encoding: [0x0c,0x43,0x00,0x04]
# CHECK-LE: twllti 3, 4 # encoding: [0x04,0x00,0x43,0x0c]
twi 2, 3, 4
# CHECK-BE: tw 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x08]
# CHECK-LE: tw 2, 3, 4 # encoding: [0x08,0x20,0x43,0x7c]
# CHECK-BE: twllt 3, 4 # encoding: [0x7c,0x43,0x20,0x08]
# CHECK-LE: twllt 3, 4 # encoding: [0x08,0x20,0x43,0x7c]
tw 2, 3, 4
# CHECK-BE: tdi 2, 3, 4 # encoding: [0x08,0x43,0x00,0x04]
# CHECK-LE: tdi 2, 3, 4 # encoding: [0x04,0x00,0x43,0x08]
# CHECK-BE: tdllti 3, 4 # encoding: [0x08,0x43,0x00,0x04]
# CHECK-LE: tdllti 3, 4 # encoding: [0x04,0x00,0x43,0x08]
tdi 2, 3, 4
# CHECK-BE: td 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x88]
# CHECK-LE: td 2, 3, 4 # encoding: [0x88,0x20,0x43,0x7c]
# CHECK-BE: tdllt 3, 4 # encoding: [0x7c,0x43,0x20,0x88]
# CHECK-LE: tdllt 3, 4 # encoding: [0x88,0x20,0x43,0x7c]
td 2, 3, 4
# Fixed-point select
@ -622,17 +622,17 @@
# CHECK-LE: extsh. 2, 3 # encoding: [0x35,0x07,0x62,0x7c]
extsh. 2, 3
# CHECK-BE: cntlzw 2, 3 # encoding: [0x7c,0x62,0x00,0x34]
# CHECK-LE: cntlzw 2, 3 # encoding: [0x34,0x00,0x62,0x7c]
# CHECK-BE: cntlz 2, 3 # encoding: [0x7c,0x62,0x00,0x34]
# CHECK-LE: cntlz 2, 3 # encoding: [0x34,0x00,0x62,0x7c]
cntlzw 2, 3
# CHECK-BE: cntlzw. 2, 3 # encoding: [0x7c,0x62,0x00,0x35]
# CHECK-LE: cntlzw. 2, 3 # encoding: [0x35,0x00,0x62,0x7c]
# CHECK-BE: cntlz. 2, 3 # encoding: [0x7c,0x62,0x00,0x35]
# CHECK-LE: cntlz. 2, 3 # encoding: [0x35,0x00,0x62,0x7c]
cntlzw. 2, 3
# CHECK-BE: cntlzw 2, 3 # encoding: [0x7c,0x62,0x00,0x34]
# CHECK-LE: cntlzw 2, 3 # encoding: [0x34,0x00,0x62,0x7c]
# CHECK-BE: cntlz 2, 3 # encoding: [0x7c,0x62,0x00,0x34]
# CHECK-LE: cntlz 2, 3 # encoding: [0x34,0x00,0x62,0x7c]
cntlz 2, 3
# CHECK-BE: cntlzw. 2, 3 # encoding: [0x7c,0x62,0x00,0x35]
# CHECK-LE: cntlzw. 2, 3 # encoding: [0x35,0x00,0x62,0x7c]
# CHECK-BE: cntlz. 2, 3 # encoding: [0x7c,0x62,0x00,0x35]
# CHECK-LE: cntlz. 2, 3 # encoding: [0x35,0x00,0x62,0x7c]
cntlz. 2, 3
cmpb 7, 21, 4
# CHECK-BE: cmpb 7, 21, 4 # encoding: [0x7e,0xa7,0x23,0xf8]

24
llvm/test/MC/PowerPC/qpx.s
View File

@ -8,9 +8,9 @@
qvfadd 3, 4, 5
# CHECK: qvfadds 3, 4, 5 # encoding: [0x00,0x64,0x28,0x2a]
qvfadds 3, 4, 5
# CHECK: qvflogical 3, 4, 5, 4 # encoding: [0x10,0x64,0x2a,0x08]
# CHECK: qvfandc 3, 4, 5 # encoding: [0x10,0x64,0x2a,0x08]
qvfandc 3, 4, 5
# CHECK: qvflogical 3, 4, 5, 1 # encoding: [0x10,0x64,0x28,0x88]
# CHECK: qvfand 3, 4, 5 # encoding: [0x10,0x64,0x28,0x88]
qvfand 3, 4, 5
# CHECK: qvfcfid 3, 5 # encoding: [0x10,0x60,0x2e,0x9c]
qvfcfid 3, 5
@ -20,11 +20,11 @@
qvfcfidu 3, 5
# CHECK: qvfcfidus 3, 5 # encoding: [0x00,0x60,0x2f,0x9c]
qvfcfidus 3, 5
# CHECK: qvflogical 3, 3, 3, 0 # encoding: [0x10,0x63,0x18,0x08]
# CHECK: qvfclr 3 # encoding: [0x10,0x63,0x18,0x08]
qvfclr 3
# CHECK: qvfcpsgn 3, 4, 5 # encoding: [0x10,0x64,0x28,0x10]
qvfcpsgn 3, 4, 5
# CHECK: qvflogical 3, 4, 4, 5 # encoding: [0x10,0x64,0x22,0x88]
# CHECK: qvfctfb 3, 4 # encoding: [0x10,0x64,0x22,0x88]
qvfctfb 3, 4
# CHECK: qvfctid 3, 5 # encoding: [0x10,0x60,0x2e,0x5c]
qvfctid 3, 5
@ -42,7 +42,7 @@
qvfctiwuz 3, 5
# CHECK: qvfctiwz 3, 5 # encoding: [0x10,0x60,0x28,0x1e]
qvfctiwz 3, 5
# CHECK: qvflogical 3, 4, 5, 9 # encoding: [0x10,0x64,0x2c,0x88]
# CHECK: qvfequ 3, 4, 5 # encoding: [0x10,0x64,0x2c,0x88]
qvfequ 3, 4, 5
# CHECK: qvflogical 3, 4, 5, 12 # encoding: [0x10,0x64,0x2e,0x08]
qvflogical 3, 4, 5, 12
@ -62,7 +62,7 @@
qvfmuls 3, 4, 6
# CHECK: qvfnabs 3, 5 # encoding: [0x10,0x60,0x29,0x10]
qvfnabs 3, 5
# CHECK: qvflogical 3, 4, 5, 14 # encoding: [0x10,0x64,0x2f,0x08]
# CHECK: qvfnand 3, 4, 5 # encoding: [0x10,0x64,0x2f,0x08]
qvfnand 3, 4, 5
# CHECK: qvfneg 3, 5 # encoding: [0x10,0x60,0x28,0x50]
qvfneg 3, 5
@ -74,13 +74,13 @@
qvfnmsub 3, 4, 6, 5
# CHECK: qvfnmsubs 3, 4, 6, 5 # encoding: [0x00,0x64,0x29,0xbc]
qvfnmsubs 3, 4, 6, 5
# CHECK: qvflogical 3, 4, 5, 8 # encoding: [0x10,0x64,0x2c,0x08]
# CHECK: qvfnor 3, 4, 5 # encoding: [0x10,0x64,0x2c,0x08]
qvfnor 3, 4, 5
# CHECK: qvflogical 3, 4, 4, 10 # encoding: [0x10,0x64,0x25,0x08]
# CHECK: qvfnot 3, 4 # encoding: [0x10,0x64,0x25,0x08]
qvfnot 3, 4
# CHECK: qvflogical 3, 4, 5, 13 # encoding: [0x10,0x64,0x2e,0x88]
# CHECK: qvforc 3, 4, 5 # encoding: [0x10,0x64,0x2e,0x88]
qvforc 3, 4, 5
# CHECK: qvflogical 3, 4, 5, 7 # encoding: [0x10,0x64,0x2b,0x88]
# CHECK: qvfor 3, 4, 5 # encoding: [0x10,0x64,0x2b,0x88]
qvfor 3, 4, 5
# CHECK: qvfperm 3, 4, 5, 6 # encoding: [0x10,0x64,0x29,0x8c]
qvfperm 3, 4, 5, 6
@ -104,7 +104,7 @@
qvfrsqrtes 3, 5
# CHECK: qvfsel 3, 4, 6, 5 # encoding: [0x10,0x64,0x29,0xae]
qvfsel 3, 4, 6, 5
# CHECK: qvflogical 3, 3, 3, 15 # encoding: [0x10,0x63,0x1f,0x88]
# CHECK: qvfset 3 # encoding: [0x10,0x63,0x1f,0x88]
qvfset 3
# CHECK: qvfsub 3, 4, 5 # encoding: [0x10,0x64,0x28,0x28]
qvfsub 3, 4, 5
@ -118,7 +118,7 @@
qvfxmul 3, 4, 6
# CHECK: qvfxmuls 3, 4, 6 # encoding: [0x00,0x64,0x01,0xa2]
qvfxmuls 3, 4, 6
# CHECK: qvflogical 3, 4, 5, 6 # encoding: [0x10,0x64,0x2b,0x08]
# CHECK: qvfxor 3, 4, 5 # encoding: [0x10,0x64,0x2b,0x08]
qvfxor 3, 4, 5
# CHECK: qvfxxcpnmadd 3, 4, 6, 5 # encoding: [0x10,0x64,0x29,0x86]
qvfxxcpnmadd 3, 4, 6, 5

24
llvm/test/MC/PowerPC/vsx.s
View File

@ -274,11 +274,11 @@
# CHECK-BE: xvminsp 7, 63, 27 # encoding: [0xf0,0xff,0xde,0x44]
# CHECK-LE: xvminsp 7, 63, 27 # encoding: [0x44,0xde,0xff,0xf0]
xvminsp 7, 63, 27
# CHECK-BE: xvcpsgndp 7, 63, 63 # encoding: [0xf0,0xff,0xff,0x86]
# CHECK-LE: xvcpsgndp 7, 63, 63 # encoding: [0x86,0xff,0xff,0xf0]
# CHECK-BE: xvmovdp 7, 63 # encoding: [0xf0,0xff,0xff,0x86]
# CHECK-LE: xvmovdp 7, 63 # encoding: [0x86,0xff,0xff,0xf0]
xvmovdp 7, 63
# CHECK-BE: xvcpsgnsp 7, 63, 63 # encoding: [0xf0,0xff,0xfe,0x86]
# CHECK-LE: xvcpsgnsp 7, 63, 63 # encoding: [0x86,0xfe,0xff,0xf0]
# CHECK-BE: xvmovsp 7, 63 # encoding: [0xf0,0xff,0xfe,0x86]
# CHECK-LE: xvmovsp 7, 63 # encoding: [0x86,0xfe,0xff,0xf0]
xvmovsp 7, 63
# CHECK-BE: xvmsubadp 7, 63, 27 # encoding: [0xf0,0xff,0xdb,0x8c]
# CHECK-LE: xvmsubadp 7, 63, 27 # encoding: [0x8c,0xdb,0xff,0xf0]
@ -424,14 +424,14 @@
# CHECK-BE: xxlxor 7, 63, 27 # encoding: [0xf0,0xff,0xdc,0xd4]
# CHECK-LE: xxlxor 7, 63, 27 # encoding: [0xd4,0xdc,0xff,0xf0]
xxlxor 7, 63, 27
# CHECK-BE: xxpermdi 7, 63, 27, 0 # encoding: [0xf0,0xff,0xd8,0x54]
# CHECK-LE: xxpermdi 7, 63, 27, 0 # encoding: [0x54,0xd8,0xff,0xf0]
# CHECK-BE: xxmrghd 7, 63, 27 # encoding: [0xf0,0xff,0xd8,0x54]
# CHECK-LE: xxmrghd 7, 63, 27 # encoding: [0x54,0xd8,0xff,0xf0]
xxmrghd 7, 63, 27
# CHECK-BE: xxmrghw 7, 63, 27 # encoding: [0xf0,0xff,0xd8,0x94]
# CHECK-LE: xxmrghw 7, 63, 27 # encoding: [0x94,0xd8,0xff,0xf0]
xxmrghw 7, 63, 27
# CHECK-BE: xxpermdi 7, 63, 27, 3 # encoding: [0xf0,0xff,0xdb,0x54]
# CHECK-LE: xxpermdi 7, 63, 27, 3 # encoding: [0x54,0xdb,0xff,0xf0]
# CHECK-BE: xxmrgld 7, 63, 27 # encoding: [0xf0,0xff,0xdb,0x54]
# CHECK-LE: xxmrgld 7, 63, 27 # encoding: [0x54,0xdb,0xff,0xf0]
xxmrgld 7, 63, 27
# CHECK-BE: xxmrglw 7, 63, 27 # encoding: [0xf0,0xff,0xd9,0x94]
# CHECK-LE: xxmrglw 7, 63, 27 # encoding: [0x94,0xd9,0xff,0xf0]
@ -445,14 +445,14 @@
# CHECK-BE: xxsldwi 7, 63, 27, 1 # encoding: [0xf0,0xff,0xd9,0x14]
# CHECK-LE: xxsldwi 7, 63, 27, 1 # encoding: [0x14,0xd9,0xff,0xf0]
xxsldwi 7, 63, 27, 1
# CHECK-BE: xxpermdi 7, 63, 63, 3 # encoding: [0xf0,0xff,0xfb,0x56]
# CHECK-LE: xxpermdi 7, 63, 63, 3 # encoding: [0x56,0xfb,0xff,0xf0]
# CHECK-BE: xxspltd 7, 63, 1 # encoding: [0xf0,0xff,0xfb,0x56]
# CHECK-LE: xxspltd 7, 63, 1 # encoding: [0x56,0xfb,0xff,0xf0]
xxspltd 7, 63, 1
# CHECK-BE: xxspltw 7, 27, 3 # encoding: [0xf0,0xe3,0xda,0x90]
# CHECK-LE: xxspltw 7, 27, 3 # encoding: [0x90,0xda,0xe3,0xf0]
xxspltw 7, 27, 3
# CHECK-BE: xxpermdi 7, 63, 63, 2 # encoding: [0xf0,0xff,0xfa,0x56]
# CHECK-LE: xxpermdi 7, 63, 63, 2 # encoding: [0x56,0xfa,0xff,0xf0]
# CHECK-BE: xxswapd 7, 63 # encoding: [0xf0,0xff,0xfa,0x56]
# CHECK-LE: xxswapd 7, 63 # encoding: [0x56,0xfa,0xff,0xf0]
xxswapd 7, 63
# Move to/from VSR