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[RISCV] Update two RISCV codegen tests after rL323991 

From the discussion in D41835 it looks possible the change will be backed out, 
but for now let's fix the RISCV tests.

llvm-svn: 324172
This commit is contained in:
Alex Bradbury 2018-02-03 13:02:30 +00:00
parent 3d5ee7aa41
commit 7c11527b03
2 changed files with 4 additions and 4 deletions
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4
llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
View File

@ -278,7 +278,7 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: sw s8, 12(sp)
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: addi a0, s3, -1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: not a1, s3
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: lui a1, 349525
@ -469,7 +469,7 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: sw s8, 12(sp)
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: addi a0, s3, -1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: not a1, s3
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: lui a1, 349525

4
llvm/test/CodeGen/RISCV/calls.ll
View File

@ -99,8 +99,8 @@ define i32 @test_call_external_many_args(i32 %a) nounwind {
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s1, 8(sp)
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: sw s1, 0(sp)
; RV32I-NEXT: sw a0, 4(sp)
; RV32I-NEXT: sw a0, 0(sp)
; RV32I-NEXT: lui a0, %hi(external_many_args)
; RV32I-NEXT: addi t0, a0, %lo(external_many_args)
; RV32I-NEXT: mv a0, s1