This patch teaches IndVarSimplify to add nuw and nsw to certain kinds
of operations that provably don't overflow. For example, we can prove
%civ.inc below does not sign-overflow. With this change,
IndVarSimplify changes %civ.inc to an add nsw.
define i32 @foo(i32* %array, i32* %length_ptr, i32 %init) {
entry:
%length = load i32* %length_ptr, !range !0
%len.sub.1 = sub i32 %length, 1
%upper = icmp slt i32 %init, %len.sub.1
br i1 %upper, label %loop, label %exit
loop:
%civ = phi i32 [ %init, %entry ], [ %civ.inc, %latch ]
%civ.inc = add i32 %civ, 1
%cmp = icmp slt i32 %civ.inc, %length
br i1 %cmp, label %latch, label %break
latch:
store i32 0, i32* %array
%check = icmp slt i32 %civ.inc, %len.sub.1
br i1 %check, label %loop, label %break
break:
ret i32 %civ.inc
exit:
ret i32 42
}
Differential Revision: http://reviews.llvm.org/D6748
llvm-svn: 225282
This commit is contained in:
Sanjoy Das
parent
4e781371d1
commit
7c0ce26614
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@ -80,6 +80,7 @@ namespace {
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void eliminateIVComparison(ICmpInst *ICmp, Value *IVOperand);
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void eliminateIVRemainder(BinaryOperator *Rem, Value *IVOperand,
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bool IsSigned);
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bool strengthenOverflowingOperation(BinaryOperator *OBO, Value *IVOperand);
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Instruction *splitOverflowIntrinsic(Instruction *IVUser,
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const DominatorTree *DT);
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@ -271,6 +272,120 @@ bool SimplifyIndvar::eliminateIVUser(Instruction *UseInst,
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return true;
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}
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/// Annotate BO with nsw / nuw if it provably does not signed-overflow /
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/// unsigned-overflow. Returns true if anything changed, false otherwise.
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bool SimplifyIndvar::strengthenOverflowingOperation(BinaryOperator *BO,
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Value *IVOperand) {
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// Currently we only handle instructions of the form "add <indvar> <value>"
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// and "sub <indvar> <value>".
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unsigned Op = BO->getOpcode();
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if (!(Op == Instruction::Add || Op == Instruction::Sub))
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return false;
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// If BO is already both nuw and nsw then there is nothing left to do
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if (BO->hasNoUnsignedWrap() && BO->hasNoSignedWrap())
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return false;
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IntegerType *IT = cast<IntegerType>(IVOperand->getType());
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Value *OtherOperand = nullptr;
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int OtherOperandIdx = -1;
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if (BO->getOperand(0) == IVOperand) {
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OtherOperand = BO->getOperand(1);
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OtherOperandIdx = 1;
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} else {
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assert(BO->getOperand(1) == IVOperand && "only other use!");
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OtherOperand = BO->getOperand(0);
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OtherOperandIdx = 0;
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}
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bool Changed = false;
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const SCEV *OtherOpSCEV = SE->getSCEV(OtherOperand);
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if (OtherOpSCEV == SE->getCouldNotCompute())
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return false;
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if (Op == Instruction::Sub) {
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// If the subtraction is of the form "sub <indvar>, <op>", then pretend it
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// is "add <indvar>, -<op>" and continue, else bail out.
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if (OtherOperandIdx != 1)
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return false;
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OtherOpSCEV = SE->getNegativeSCEV(OtherOpSCEV);
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}
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const SCEV *IVOpSCEV = SE->getSCEV(IVOperand);
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const SCEV *ZeroSCEV = SE->getConstant(IVOpSCEV->getType(), 0);
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if (!BO->hasNoSignedWrap()) {
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// Upgrade the add to an "add nsw" if we can prove that it will never
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// sign-overflow or sign-underflow.
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const SCEV *SignedMax =
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SE->getConstant(APInt::getSignedMaxValue(IT->getBitWidth()));
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const SCEV *SignedMin =
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SE->getConstant(APInt::getSignedMinValue(IT->getBitWidth()));
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// The addition "IVOperand + OtherOp" does not sign-overflow if the result
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// is sign-representable in 2's complement in the given bit-width.
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//
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// If OtherOp is SLT 0, then for an IVOperand in [SignedMin - OtherOp,
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// SignedMax], "IVOperand + OtherOp" is in [SignedMin, SignedMax + OtherOp].
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// Everything in [SignedMin, SignedMax + OtherOp] is representable since
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// SignedMax + OtherOp is at least -1.
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//
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// If OtherOp is SGE 0, then for an IVOperand in [SignedMin, SignedMax -
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// OtherOp], "IVOperand + OtherOp" is in [SignedMin + OtherOp, SignedMax].
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// Everything in [SignedMin + OtherOp, SignedMax] is representable since
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// SignedMin + OtherOp is at most -1.
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//
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// It follows that for all values of IVOperand in [SignedMin - smin(0,
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// OtherOp), SignedMax - smax(0, OtherOp)] the result of the add is
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// representable (i.e. there is no sign-overflow).
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const SCEV *UpperDelta = SE->getSMaxExpr(ZeroSCEV, OtherOpSCEV);
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const SCEV *UpperLimit = SE->getMinusSCEV(SignedMax, UpperDelta);
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bool NeverSignedOverflows =
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SE->isKnownPredicate(ICmpInst::ICMP_SLE, IVOpSCEV, UpperLimit);
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if (NeverSignedOverflows) {
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const SCEV *LowerDelta = SE->getSMinExpr(ZeroSCEV, OtherOpSCEV);
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const SCEV *LowerLimit = SE->getMinusSCEV(SignedMin, LowerDelta);
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bool NeverSignedUnderflows =
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SE->isKnownPredicate(ICmpInst::ICMP_SGE, IVOpSCEV, LowerLimit);
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if (NeverSignedUnderflows) {
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BO->setHasNoSignedWrap(true);
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Changed = true;
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}
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}
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}
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if (!BO->hasNoUnsignedWrap()) {
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// Upgrade the add computing "IVOperand + OtherOp" to an "add nuw" if we can
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// prove that it will never unsigned-overflow (i.e. the result will always
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// be representable in the given bit-width).
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//
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// "IVOperand + OtherOp" is unsigned-representable in 2's complement iff it
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// does not produce a carry. "IVOperand + OtherOp" produces no carry iff
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// IVOperand ULE (UnsignedMax - OtherOp).
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const SCEV *UnsignedMax =
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SE->getConstant(APInt::getMaxValue(IT->getBitWidth()));
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const SCEV *UpperLimit = SE->getMinusSCEV(UnsignedMax, OtherOpSCEV);
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bool NeverUnsignedOverflows =
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SE->isKnownPredicate(ICmpInst::ICMP_ULE, IVOpSCEV, UpperLimit);
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if (NeverUnsignedOverflows) {
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BO->setHasNoUnsignedWrap(true);
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Changed = true;
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}
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}
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return Changed;
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}
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/// \brief Split sadd.with.overflow into add + sadd.with.overflow to allow
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/// analysis and optimization.
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///
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@ -430,6 +545,16 @@ void SimplifyIndvar::simplifyUsers(PHINode *CurrIV, IVVisitor *V) {
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pushIVUsers(IVOperand, Simplified, SimpleIVUsers);
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continue;
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}
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if (BinaryOperator *BO = dyn_cast<BinaryOperator>(UseOper.first)) {
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if (isa<OverflowingBinaryOperator>(BO) &&
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strengthenOverflowingOperation(BO, IVOperand)) {
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// re-queue uses of the now modified binary operator and fall
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// through to the checks that remain.
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pushIVUsers(IVOperand, Simplified, SimpleIVUsers);
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}
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}
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CastInst *Cast = dyn_cast<CastInst>(UseOper.first);
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if (V && Cast) {
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V->visitCast(Cast);
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@ -83,7 +83,7 @@ for.body: ; preds = %for.body, %entry
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; CHECK-UNRL: %add12 = fadd <2 x double> %add7, %mul11
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; CHECK-UNRL: %4 = bitcast double* %arrayidx14 to <2 x double>*
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; CHECK-UNRL: store <2 x double> %add12, <2 x double>* %4, align 8
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; CHECK-UNRL: %indvars.iv.next.1 = add i64 %indvars.iv, 2
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; CHECK-UNRL: %indvars.iv.next.1 = add nsw i64 %indvars.iv, 2
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; CHECK-UNRL: %lftr.wideiv.1 = trunc i64 %indvars.iv.next.1 to i32
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; CHECK-UNRL: %exitcond.1 = icmp eq i32 %lftr.wideiv.1, 10
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; CHECK-UNRL: br i1 %exitcond.1, label %for.end, label %for.body
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@ -17,7 +17,7 @@ for.body11: ; preds = %entry
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for.body153: ; preds = %for.body153, %for.body11
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br i1 undef, label %for.body170, label %for.body153
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; CHECK: add nsw i64 %indvars.iv, 1
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; CHECK: add nuw nsw i64 %indvars.iv, 1
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; CHECK: sub nsw i64 %indvars.iv, 2
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; CHECK: sub nsw i64 4, %indvars.iv
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; CHECK: mul nsw i64 %indvars.iv, 8
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@ -0,0 +1,214 @@
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; RUN: opt < %s -indvars -S | FileCheck %s
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define i32 @test.signed.add.0(i32* %array, i32 %length, i32 %init) {
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; CHECK-LABEL: @test.signed.add.0
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entry:
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%upper = icmp slt i32 %init, %length
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br i1 %upper, label %loop, label %exit
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loop:
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; CHECK-LABEL: loop
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%civ = phi i32 [ %init, %entry ], [ %civ.inc, %latch ]
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%civ.inc = add i32 %civ, 1
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; CHECK: %civ.inc = add nsw i32 %civ, 1
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%cmp = icmp slt i32 %civ.inc, %length
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br i1 %cmp, label %latch, label %break
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latch:
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store i32 0, i32* %array
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%check = icmp slt i32 %civ.inc, %length
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br i1 %check, label %loop, label %break
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break:
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ret i32 %civ.inc
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exit:
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ret i32 42
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}
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define i32 @test.signed.add.1(i32* %array, i32 %length, i32 %init) {
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; CHECK-LABEL: @test.signed.add.1
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entry:
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%upper = icmp sle i32 %init, %length
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br i1 %upper, label %loop, label %exit
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loop:
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; CHECK-LABEL: loop
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%civ = phi i32 [ %init, %entry ], [ %civ.inc, %latch ]
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%civ.inc = add i32 %civ, 1
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; CHECK: %civ.inc = add i32 %civ, 1
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%cmp = icmp slt i32 %civ.inc, %length
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br i1 %cmp, label %latch, label %break
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latch:
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store i32 0, i32* %array
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%check = icmp slt i32 %civ.inc, %length
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br i1 %check, label %loop, label %break
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break:
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ret i32 %civ.inc
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exit:
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ret i32 42
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}
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define i32 @test.signed.sub.0(i32* %array, i32 %length, i32 %init) {
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; CHECK-LABEL: @test.signed.sub.0
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entry:
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%upper = icmp sgt i32 %init, %length
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br i1 %upper, label %loop, label %exit
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loop:
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; CHECK-LABEL: loop
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%civ = phi i32 [ %init, %entry ], [ %civ.inc, %latch ]
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%civ.inc = sub i32 %civ, 1
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; CHECK: %civ.inc = sub nsw i32 %civ, 1
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%cmp = icmp slt i32 %civ.inc, %length
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br i1 %cmp, label %latch, label %break
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latch:
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store i32 0, i32* %array
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%check = icmp sgt i32 %civ.inc, %length
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br i1 %check, label %loop, label %break
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break:
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ret i32 %civ.inc
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exit:
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ret i32 42
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}
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define i32 @test.signed.sub.1(i32* %array, i32 %length, i32 %init) {
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; CHECK-LABEL: @test.signed.sub.1
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entry:
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%upper = icmp sgt i32 %init, %length
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br i1 %upper, label %loop, label %exit
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loop:
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; CHECK-LABEL: loop
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%civ = phi i32 [ %init, %entry ], [ %civ.inc, %latch ]
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%civ.inc = sub i32 %civ, 1
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; CHECK: %civ.inc = sub i32 %civ, 1
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%cmp = icmp slt i32 %civ.inc, %length
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br i1 %cmp, label %latch, label %break
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latch:
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store i32 0, i32* %array
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%check = icmp sge i32 %civ.inc, %length
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br i1 %check, label %loop, label %break
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break:
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ret i32 %civ.inc
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exit:
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ret i32 42
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}
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define i32 @test.unsigned.add.0(i32* %array, i32 %length, i32 %init) {
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; CHECK-LABEL: @test.unsigned.add.0
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entry:
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%upper = icmp ult i32 %init, %length
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br i1 %upper, label %loop, label %exit
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loop:
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; CHECK-LABEL: loop
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%civ = phi i32 [ %init, %entry ], [ %civ.inc, %latch ]
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%civ.inc = add i32 %civ, 1
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; CHECK: %civ.inc = add nuw i32 %civ, 1
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%cmp = icmp slt i32 %civ.inc, %length
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br i1 %cmp, label %latch, label %break
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latch:
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store i32 0, i32* %array
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%check = icmp ult i32 %civ.inc, %length
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br i1 %check, label %loop, label %break
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break:
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ret i32 %civ.inc
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exit:
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ret i32 42
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}
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define i32 @test.unsigned.add.1(i32* %array, i32 %length, i32 %init) {
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; CHECK-LABEL: @test.unsigned.add.1
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entry:
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%upper = icmp ule i32 %init, %length
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br i1 %upper, label %loop, label %exit
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loop:
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; CHECK-LABEL: loop
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%civ = phi i32 [ %init, %entry ], [ %civ.inc, %latch ]
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%civ.inc = add i32 %civ, 1
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; CHECK: %civ.inc = add i32 %civ, 1
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%cmp = icmp slt i32 %civ.inc, %length
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br i1 %cmp, label %latch, label %break
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latch:
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store i32 0, i32* %array
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%check = icmp ult i32 %civ.inc, %length
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br i1 %check, label %loop, label %break
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break:
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ret i32 %civ.inc
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exit:
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ret i32 42
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}
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define i32 @test.unsigned.sub.0(i32* %array, i32* %length_ptr, i32 %init) {
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; CHECK-LABEL: @test.unsigned.sub.0
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entry:
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%length = load i32* %length_ptr, !range !0
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%upper = icmp ult i32 %init, %length
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br i1 %upper, label %loop, label %exit
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loop:
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; CHECK-LABEL: loop
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%civ = phi i32 [ %init, %entry ], [ %civ.inc, %latch ]
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%civ.inc = sub i32 %civ, 2
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; CHECK: %civ.inc = sub nuw i32 %civ, 2
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%cmp = icmp slt i32 %civ.inc, %length
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br i1 %cmp, label %latch, label %break
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latch:
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store i32 0, i32* %array
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%check = icmp ult i32 %civ.inc, %length
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br i1 %check, label %loop, label %break
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break:
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ret i32 %civ.inc
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exit:
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ret i32 42
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}
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define i32 @test.unsigned.sub.1(i32* %array, i32* %length_ptr, i32 %init) {
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; CHECK-LABEL: @test.unsigned.sub.1
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entry:
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%length = load i32* %length_ptr, !range !1
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%upper = icmp ult i32 %init, %length
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br i1 %upper, label %loop, label %exit
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loop:
|
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; CHECK-LABEL: loop
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%civ = phi i32 [ %init, %entry ], [ %civ.inc, %latch ]
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%civ.inc = sub i32 %civ, 2
|
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; CHECK: %civ.inc = sub i32 %civ, 2
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%cmp = icmp slt i32 %civ.inc, %length
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br i1 %cmp, label %latch, label %break
|
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|
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latch:
|
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store i32 0, i32* %array
|
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%check = icmp ult i32 %civ.inc, %length
|
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br i1 %check, label %loop, label %break
|
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|
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break:
|
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ret i32 %civ.inc
|
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exit:
|
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ret i32 42
|
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}
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|
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!0 = !{i32 0, i32 2}
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!1 = !{i32 0, i32 42}
|
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