Legalizer: Make bswap promotion safe for vectors.
llvm-svn: 209202
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@ -268,9 +268,9 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
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EVT NVT = Op.getValueType();
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SDLoc dl(N);
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unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
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unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
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return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
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DAG.getConstant(DiffBits, TLI.getPointerTy()));
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DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
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}
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SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
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@ -122,6 +122,23 @@ entry:
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; CHECK-AVX2-NEXT: retq
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}
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declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>)
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define <4 x i16> @test7(<4 x i16> %v) #0 {
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entry:
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%r = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %v)
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ret <4 x i16> %r
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; CHECK-SSSE3-LABEL: @test7
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; CHECK-SSSE3: pshufb
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; CHECK-SSSE3: psrld $16
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; CHECK-SSSE3-NEXT: retq
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; CHECK-AVX2-LABEL: @test7
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; CHECK-AVX2: vpshufb
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; CHECK-AVX2: vpsrld $16
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; CHECK-AVX2-NEXT: retq
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}
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attributes #0 = { nounwind uwtable }
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