parent
2091a36631
commit
7bbdae53d6
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@ -1414,7 +1414,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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Tmp2 = SelectExpr(N.getOperand(1));
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if (N.getOpcode() == ISD::ADD_PARTS) {
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bool ME, ZE;
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bool ME = false, ZE = false;
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if (isIntImmediate(N.getOperand(3), Tmp3)) {
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ME = (signed)Tmp3 == -1;
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ZE = Tmp3 == 0;
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@ -896,7 +896,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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unsigned Opc;
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switch (N->getValueType(0)) {
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default: assert(0 && "Unknown type to ISD::SDIV"); break;
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default: assert(0 && "Unknown type to ISD::SDIV");
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case MVT::i32: Opc = PPC::DIVW; break;
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case MVT::f32: Opc = PPC::FDIVS; break;
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case MVT::f64: Opc = PPC::FDIV; break;
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@ -1135,7 +1135,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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SDOperand LHSH = Select(N->getOperand(1));
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unsigned Imm;
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bool ME, ZE;
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bool ME = false, ZE = false;
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if (isIntImmediate(N->getOperand(3), Imm)) {
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ME = (signed)Imm == -1;
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ZE = Imm == 0;
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