diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
index 102b4b3845d7..3187e4a349cc 100644
--- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
@@ -1414,7 +1414,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     Tmp2 = SelectExpr(N.getOperand(1));
     
     if (N.getOpcode() == ISD::ADD_PARTS) {
-      bool ME, ZE;
+      bool ME = false, ZE = false;
       if (isIntImmediate(N.getOperand(3), Tmp3)) {
         ME = (signed)Tmp3 == -1;
         ZE = Tmp3 == 0;
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index a3391f1cfbb5..8c1e6cbf8bf3 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -896,7 +896,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
     
     unsigned Opc;
     switch (N->getValueType(0)) {
-    default: assert(0 && "Unknown type to ISD::SDIV"); break;
+    default: assert(0 && "Unknown type to ISD::SDIV");
     case MVT::i32: Opc = PPC::DIVW; break;
     case MVT::f32: Opc = PPC::FDIVS; break;
     case MVT::f64: Opc = PPC::FDIV; break;
@@ -1135,7 +1135,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
     SDOperand LHSH = Select(N->getOperand(1));
    
     unsigned Imm;
-    bool ME, ZE;
+    bool ME = false, ZE = false;
     if (isIntImmediate(N->getOperand(3), Imm)) {
       ME = (signed)Imm == -1;
       ZE = Imm == 0;