AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|EXTRACT}_VECTOR_ELT
llvm-svn: 327269
This commit is contained in:
Matt Arsenault
parent
c0aefd561e
commit
7b9ed89dcf
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@ -107,6 +107,17 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const SISubtarget &ST,
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setAction({G_LOAD, 1, S64}, Legal);
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setAction({G_STORE, 1, S64}, Legal);
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for (unsigned Op : {G_EXTRACT_VECTOR_ELT, G_INSERT_VECTOR_ELT}) {
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getActionDefinitionsBuilder(Op)
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.legalIf([=](const LegalityQuery &Query) {
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const LLT &VecTy = Query.Types[1];
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const LLT &IdxTy = Query.Types[2];
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return VecTy.getSizeInBits() % 32 == 0 &&
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VecTy.getSizeInBits() <= 512 &&
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IdxTy.getSizeInBits() == 32;
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});
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}
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// FIXME: Doesn't handle extract of illegal sizes.
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getActionDefinitionsBuilder(G_EXTRACT)
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.unsupportedIf([=](const LegalityQuery &Query) {
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@ -50,6 +50,24 @@ AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI)
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}
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static bool isConstant(const MachineOperand &MO, int64_t &C) {
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const MachineFunction *MF = MO.getParent()->getParent()->getParent();
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const MachineRegisterInfo &MRI = MF->getRegInfo();
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const MachineInstr *Def = MRI.getVRegDef(MO.getReg());
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if (!Def)
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return false;
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if (Def->getOpcode() == AMDGPU::G_CONSTANT) {
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C = Def->getOperand(1).getCImm()->getSExtValue();
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return true;
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}
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if (Def->getOpcode() == AMDGPU::COPY)
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return isConstant(Def->getOperand(1), C);
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return false;
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}
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unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
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const RegisterBank &Src,
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unsigned Size) const {
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@ -415,6 +433,47 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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OpdsMapping[3] = AMDGPU::getValueMapping(Op3Bank, Size);
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break;
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}
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case AMDGPU::G_EXTRACT_VECTOR_ELT: {
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unsigned IdxOp = 2;
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int64_t Imm;
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// XXX - Do we really need to fully handle these? The constant case should
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// be legalized away before RegBankSelect?
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unsigned OutputBankID = isSALUMapping(MI) && isConstant(MI.getOperand(IdxOp), Imm) ?
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AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
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unsigned IdxBank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
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OpdsMapping[0] = AMDGPU::getValueMapping(OutputBankID, MRI.getType(MI.getOperand(0).getReg()).getSizeInBits());
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OpdsMapping[1] = AMDGPU::getValueMapping(OutputBankID, MRI.getType(MI.getOperand(1).getReg()).getSizeInBits());
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// The index can be either if the source vector is VGPR.
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OpdsMapping[2] = AMDGPU::getValueMapping(IdxBank, MRI.getType(MI.getOperand(2).getReg()).getSizeInBits());
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break;
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}
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case AMDGPU::G_INSERT_VECTOR_ELT: {
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// XXX - Do we really need to fully handle these? The constant case should
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// be legalized away before RegBankSelect?
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int64_t Imm;
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unsigned IdxOp = MI.getOpcode() == AMDGPU::G_EXTRACT_VECTOR_ELT ? 2 : 3;
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unsigned BankID = isSALUMapping(MI) && isConstant(MI.getOperand(IdxOp), Imm) ?
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AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
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// TODO: Can do SGPR indexing, which would obviate the need for the
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// isConstant check.
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
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OpdsMapping[i] = AMDGPU::getValueMapping(BankID, Size);
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}
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break;
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}
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case AMDGPU::G_INTRINSIC: {
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switch(MI.getOperand(1).getIntrinsicID()) {
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default:
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@ -0,0 +1,180 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
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---
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name: extract_vector_elt_0_v2i32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: extract_vector_elt_0_v2i32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_CONSTANT i32 0
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%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
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$vgpr0 = COPY %2
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...
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---
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name: extract_vector_elt_0_v3i32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2
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; CHECK-LABEL: name: extract_vector_elt_0_v3i32
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; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<3 x s32>), [[C]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
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%1:_(s32) = G_CONSTANT i32 0
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%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
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$vgpr0 = COPY %2
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...
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---
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name: extract_vector_elt_0_v4i32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK-LABEL: name: extract_vector_elt_0_v4i32
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%1:_(s32) = G_CONSTANT i32 0
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%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
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$vgpr0 = COPY %2
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...
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---
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name: extract_vector_elt_0_v5i32
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: extract_vector_elt_0_v5i32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[MV:%[0-9]+]]:_(<5 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<5 x s32>), [[C]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(<5 x s32>) = G_MERGE_VALUES %0, %0, %0, %0, %0
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
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$vgpr0 = COPY %3
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...
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---
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name: extract_vector_elt_0_v6i32
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: extract_vector_elt_0_v6i32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[MV:%[0-9]+]]:_(<6 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<6 x s32>), [[C]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(<6 x s32>) = G_MERGE_VALUES %0, %0, %0, %0, %0, %0
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
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$vgpr0 = COPY %3
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...
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---
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name: extract_vector_elt_0_v7i32
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: extract_vector_elt_0_v7i32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[MV:%[0-9]+]]:_(<7 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<7 x s32>), [[C]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(<7 x s32>) = G_MERGE_VALUES %0, %0, %0, %0, %0, %0, %0
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
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$vgpr0 = COPY %3
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...
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---
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name: extract_vector_elt_0_v8i32
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: extract_vector_elt_0_v8i32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[MV:%[0-9]+]]:_(<8 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<8 x s32>), [[C]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(<8 x s32>) = G_MERGE_VALUES %0, %0, %0, %0, %0, %0, %0, %0
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
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$vgpr0 = COPY %3
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...
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---
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name: extract_vector_elt_0_v16i32
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: extract_vector_elt_0_v16i32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[MV:%[0-9]+]]:_(<16 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<16 x s32>), [[C]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(<16 x s32>) = G_MERGE_VALUES %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
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$vgpr0 = COPY %3
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...
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---
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name: extract_vector_elt_var_v2i32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2
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; CHECK-LABEL: name: extract_vector_elt_var_v2i32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[COPY1]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(s32) = COPY $vgpr2
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%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
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$vgpr0 = COPY %2
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...
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---
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name: extract_vector_elt_var_v8i32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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; CHECK-LABEL: name: extract_vector_elt_var_v8i32
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; CHECK: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<8 x s32>), [[COPY1]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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%0:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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%1:_(s32) = COPY $vgpr2
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%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
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$vgpr0 = COPY %2
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...
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@ -0,0 +1,21 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
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---
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name: insert_vector_elt_0_v2i32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2
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; CHECK-LABEL: name: insert_vector_elt_0_v2i32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[C]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[IVEC]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(s32) = COPY $vgpr2
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
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$vgpr0_vgpr1 = COPY %3
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...
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@ -0,0 +1,39 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
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---
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name: extract_vector_elt_0_v2i32_s
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: extract_vector_elt_0_v2i32_s
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; CHECK: [[COPY:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[EVEC:%[0-9]+]]:sgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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%0:_(<2 x s32>) = COPY $sgpr0_sgpr1
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%1:_(s32) = G_CONSTANT i32 0
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%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
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$vgpr0 = COPY %2
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...
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---
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name: extract_vector_elt_0_v4i32_s
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK-LABEL: name: extract_vector_elt_0_v4i32_s
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; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[EVEC:%[0-9]+]]:sgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
|
||||
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:_(s32) = G_CONSTANT i32 0
|
||||
%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
|
||||
$vgpr0 = COPY %2
|
||||
...
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
|
||||
|
||||
---
|
||||
name: insert_vector_elt_v4i32_s_s_k
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5
|
||||
; CHECK-LABEL: name: insert_vector_elt_v4i32_s_s_k
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[IVEC:%[0-9]+]]:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[C]](s32)
|
||||
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
|
||||
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:_(s32) = COPY $sgpr5
|
||||
%2:_(s32) = G_CONSTANT i32 0
|
||||
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
|
||||
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: insert_vector_elt_v4i32_v_s_k
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr5
|
||||
; CHECK-LABEL: name: insert_vector_elt_v4i32_v_s_k
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
|
||||
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY2]](s32), [[COPY3]](s32)
|
||||
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
|
||||
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
%1:_(s32) = COPY $sgpr5
|
||||
%2:_(s32) = G_CONSTANT i32 0
|
||||
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
|
||||
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: insert_vector_elt_v4i32_s_v_k
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr5
|
||||
; CHECK-LABEL: name: insert_vector_elt_v4i32_s_v_k
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
|
||||
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY2]], [[COPY1]](s32), [[COPY3]](s32)
|
||||
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
|
||||
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:_(s32) = COPY $vgpr2
|
||||
%2:_(s32) = G_CONSTANT i32 0
|
||||
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
|
||||
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: insert_vector_elt_var_v4i32_s_s_s
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, $sgpr6
|
||||
; CHECK-LABEL: name: insert_vector_elt_var_v4i32_s_s_s
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
|
||||
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY4]](s32), [[COPY5]](s32)
|
||||
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
|
||||
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:_(s32) = COPY $sgpr5
|
||||
%2:_(s32) = COPY $sgpr6
|
||||
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
|
||||
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: insert_vector_elt_var_v4i32_s_s_v
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, $vgpr6
|
||||
; CHECK-LABEL: name: insert_vector_elt_var_v4i32_s_s_v
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
|
||||
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY4]](s32), [[COPY2]](s32)
|
||||
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
|
||||
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:_(s32) = COPY $sgpr5
|
||||
%2:_(s32) = COPY $vgpr6
|
||||
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
|
||||
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: insert_vector_elt_var_v4i32_v_s_v
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr5, $vgpr6
|
||||
; CHECK-LABEL: name: insert_vector_elt_var_v4i32_v_s_v
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY3]](s32), [[COPY2]](s32)
|
||||
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
|
||||
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
%1:_(s32) = COPY $sgpr5
|
||||
%2:_(s32) = COPY $vgpr6
|
||||
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
|
||||
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: insert_vector_elt_var_v4i32_v_v_v
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr5, $vgpr6
|
||||
; CHECK-LABEL: name: insert_vector_elt_var_v4i32_v_v_v
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
|
||||
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[COPY2]](s32)
|
||||
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
|
||||
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
%1:_(s32) = COPY $vgpr5
|
||||
%2:_(s32) = COPY $vgpr6
|
||||
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
|
||||
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
|
||||
...
|
||||
Loading…
Reference in New Issue