From 7b7b99c74a3440e16ff37375f100e3a30077106d Mon Sep 17 00:00:00 2001 From: Nadav Rotem Date: Tue, 24 Apr 2012 11:27:53 +0000 Subject: [PATCH] AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8 immediate. We can't use it here because the shuffle code does not check that the lower part of the word is identical to the upper part. llvm-svn: 155440 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 6 ------ 1 file changed, 6 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index e16367ab42d0..8a11b45f0e71 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -5443,12 +5443,6 @@ static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp, ISDNo = X86ISD::BLENDPD; OpTy = MVT::v4f64; break; - case MVT::v16i16: - if (!Subtarget->hasAVX2()) - return SDValue(); - ISDNo = X86ISD::BLENDPW; - OpTy = MVT::v16i16; - break; } assert(ISDNo && "Invalid Op Number");