Fix AVX512 vector sqrt assembly strings.
llvm-svn: 201681
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@ -3275,25 +3275,25 @@ multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
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Intrinsic V16F32Int, Intrinsic V8F64Int,
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Intrinsic V16F32Int, Intrinsic V8F64Int,
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OpndItins itins_s, OpndItins itins_d> {
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OpndItins itins_s, OpndItins itins_d> {
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def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
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def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
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!strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
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!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
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[(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
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[(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
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EVEX, EVEX_V512;
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EVEX, EVEX_V512;
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let mayLoad = 1 in
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let mayLoad = 1 in
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def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
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def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
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!strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
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!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
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[(set VR512:$dst,
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[(set VR512:$dst,
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(OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
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(OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
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itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
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itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
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def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
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def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
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!strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
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[(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
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EVEX, EVEX_V512;
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EVEX, EVEX_V512;
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let mayLoad = 1 in
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let mayLoad = 1 in
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def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
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def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
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!strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR512:$dst, (OpNode
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[(set VR512:$dst, (OpNode
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(v8f64 (bitconvert (memopv16f32 addr:$src)))))],
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(v8f64 (bitconvert (memopv16f32 addr:$src)))))],
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itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
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itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
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@ -224,6 +224,24 @@ define float @sqrtC(float %a) nounwind {
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ret float %b
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ret float %b
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}
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}
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; CHECK-LABEL: sqrtD
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; CHECK: vsqrtps {{.*}}
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; CHECK: ret
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declare <16 x float> @llvm.sqrt.v16f32(<16 x float>)
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define <16 x float> @sqrtD(<16 x float> %a) nounwind {
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%b = call <16 x float> @llvm.sqrt.v16f32(<16 x float> %a)
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ret <16 x float> %b
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}
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; CHECK-LABEL: sqrtE
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; CHECK: vsqrtpd {{.*}}
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; CHECK: ret
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declare <8 x double> @llvm.sqrt.v8f64(<8 x double>)
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define <8 x double> @sqrtE(<8 x double> %a) nounwind {
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%b = call <8 x double> @llvm.sqrt.v8f64(<8 x double> %a)
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ret <8 x double> %b
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}
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; CHECK-LABEL: fadd_broadcast
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; CHECK-LABEL: fadd_broadcast
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; CHECK: LCP{{.*}}(%rip){1to16}, %zmm0, %zmm0
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; CHECK: LCP{{.*}}(%rip){1to16}, %zmm0, %zmm0
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; CHECK: ret
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; CHECK: ret
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