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Fix AVX512 vector sqrt assembly strings. 

llvm-svn: 201681
This commit is contained in:
Cameron McInally 2014-02-19 15:16:09 +00:00
parent 31043152d3
commit 7b544f0297
2 changed files with 22 additions and 4 deletions
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8
llvm/lib/Target/X86/X86InstrAVX512.td
View File

@ -3275,25 +3275,25 @@ multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Intrinsic V16F32Int, Intrinsic V8F64Int, Intrinsic V16F32Int, Intrinsic V8F64Int,
OpndItins itins_s, OpndItins itins_d> { OpndItins itins_s, OpndItins itins_d> {
def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src), def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
!strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
[(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>, [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
EVEX, EVEX_V512; EVEX, EVEX_V512;
let mayLoad = 1 in let mayLoad = 1 in
def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src), def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
!strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
[(set VR512:$dst, [(set VR512:$dst,
(OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))], (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>; itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src), def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
!strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
[(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>, [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
EVEX, EVEX_V512; EVEX, EVEX_V512;
let mayLoad = 1 in let mayLoad = 1 in
def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src), def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
!strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
[(set VR512:$dst, (OpNode [(set VR512:$dst, (OpNode
(v8f64 (bitconvert (memopv16f32 addr:$src)))))], (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>; itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;

18
llvm/test/CodeGen/X86/avx512-arith.ll
View File

@ -224,6 +224,24 @@ define float @sqrtC(float %a) nounwind {
ret float %b ret float %b
} }
; CHECK-LABEL: sqrtD
; CHECK: vsqrtps {{.*}}
; CHECK: ret
declare <16 x float> @llvm.sqrt.v16f32(<16 x float>)
define <16 x float> @sqrtD(<16 x float> %a) nounwind {
%b = call <16 x float> @llvm.sqrt.v16f32(<16 x float> %a)
ret <16 x float> %b
}
; CHECK-LABEL: sqrtE
; CHECK: vsqrtpd {{.*}}
; CHECK: ret
declare <8 x double> @llvm.sqrt.v8f64(<8 x double>)
define <8 x double> @sqrtE(<8 x double> %a) nounwind {
%b = call <8 x double> @llvm.sqrt.v8f64(<8 x double> %a)
ret <8 x double> %b
}
; CHECK-LABEL: fadd_broadcast ; CHECK-LABEL: fadd_broadcast
; CHECK: LCP{{.*}}(%rip){1to16}, %zmm0, %zmm0 ; CHECK: LCP{{.*}}(%rip){1to16}, %zmm0, %zmm0
; CHECK: ret ; CHECK: ret