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Remove non-DebugLoc versions of getMergeValues, ZeroExtendInReg. 

llvm-svn: 63800
This commit is contained in:
Dale Johannesen 2009-02-05 00:20:09 +00:00
parent fff09f335d
commit 7ae8c8b108
7 changed files with 42 additions and 55 deletions
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2
llvm/include/llvm/CodeGen/SelectionDAG.h
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@ -371,7 +371,6 @@ public:
/// getZeroExtendInReg - Return the expression required to zero extend the Op
/// value assuming it was the smaller SrcTy value.
SDValue getZeroExtendInReg(SDValue Op, MVT SrcTy);
SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT SrcTy);
/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
@ -537,7 +536,6 @@ public:
bool ReadMem = true, bool WriteMem = true);
/// getMergeValues - Create a MERGE_VALUES node from the given operands.
SDValue getMergeValues(const SDValue *Ops, unsigned NumOps);
SDValue getMergeValues(const SDValue *Ops, unsigned NumOps, DebugLoc dl);
/// getCall - Create a CALL node from the given information.

14
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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@ -389,7 +389,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
DAG.getValueType(N->getOperand(0).getValueType()));
if (N->getOpcode() == ISD::ZERO_EXTEND)
return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
return Res;
}
@ -573,7 +573,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
// Calculate the overflow flag: zero extend the arithmetic result from
// the original type.
SDValue Ofl = DAG.getZeroExtendInReg(Res, OVT);
SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
// Overflowed if and only if this is not equal to Res.
Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
@ -853,10 +853,11 @@ SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
SDValue NewOps[6];
DebugLoc dl = N->getDebugLoc();
NewOps[0] = N->getOperand(0);
for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
SDValue Flag = GetPromotedInteger(N->getOperand(i));
NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
}
return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
array_lengthof(NewOps));
@ -941,9 +942,10 @@ SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
}
SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
SDValue Op = GetPromotedInteger(N->getOperand(0));
Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
}
@ -1905,7 +1907,7 @@ void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
SplitInteger(Res, Lo, Hi);
unsigned ExcessBits =
Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits));
}
}

6
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
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@ -231,8 +231,9 @@ private:
/// final size.
SDValue SExtPromotedInteger(SDValue Op) {
MVT OldVT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
Op = GetPromotedInteger(Op);
return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
DAG.getValueType(OldVT));
}
@ -240,8 +241,9 @@ private:
/// final size.
SDValue ZExtPromotedInteger(SDValue Op) {
MVT OldVT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
Op = GetPromotedInteger(Op);
return DAG.getZeroExtendInReg(Op, OldVT);
return DAG.getZeroExtendInReg(Op, dl, OldVT);
}
// Integer Result Promotion.

20
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -829,14 +829,6 @@ void SelectionDAG::clear() {
Root = getEntryNode();
}
SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) {
if (Op.getValueType() == VT) return Op;
APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(),
VT.getSizeInBits());
return getNode(ISD::AND, Op.getValueType(), Op,
getConstant(Imm, Op.getValueType()));
}
SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) {
if (Op.getValueType() == VT) return Op;
APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(),
@ -3463,18 +3455,6 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
/// getMergeValues - Create a MERGE_VALUES node from the given operands.
/// Allowed to return something different (and simpler) if Simplify is true.
SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps) {
if (NumOps == 1)
return Ops[0];
SmallVector<MVT, 4> VTs;
VTs.reserve(NumOps);
for (unsigned i = 0; i < NumOps; ++i)
VTs.push_back(Ops[i].getValueType());
return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps);
}
/// DebugLoc-aware version.
SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps,
DebugLoc dl) {
if (NumOps == 1)

8
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
View File

@ -882,7 +882,8 @@ SDValue SelectionDAGLowering::getValue(const Value *V) {
for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
Constants.push_back(SDValue(Val, i));
}
return DAG.getMergeValues(&Constants[0], Constants.size());
return DAG.getMergeValues(&Constants[0], Constants.size(),
getCurDebugLoc());
}
if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
@ -904,7 +905,7 @@ SDValue SelectionDAGLowering::getValue(const Value *V) {
else
Constants[i] = DAG.getConstant(0, EltVT);
}
return DAG.getMergeValues(&Constants[0], NumElts);
return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
}
const VectorType *VecTy = cast<VectorType>(V->getType());
@ -5786,7 +5787,8 @@ LowerArguments(BasicBlock *LLVMBB) {
ComputeValueVTs(TLI, AI->getType(), ValueVTs);
unsigned NumValues = ValueVTs.size();
if (!AI->use_empty()) {
SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues));
SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
SDL->getCurDebugLoc()));
// If this argument is live outside of the entry block, insert a copy from
// whereever we got it to the vreg that other BB's will reference it as.
DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);

5
llvm/lib/Target/PIC16/PIC16ISelLowering.cpp
View File

@ -926,6 +926,7 @@ PIC16TargetLowering::LowerCallReturn(SDValue Op, SDValue Chain,
SDValue InFlag,
SelectionDAG &DAG) {
CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
DebugLoc dl = TheCall->getDebugLoc();
// Currently handling primitive types only. They will come in
// i8 parts
unsigned RetVals = TheCall->getNumRetVals();
@ -948,7 +949,7 @@ PIC16TargetLowering::LowerCallReturn(SDValue Op, SDValue Chain,
for(unsigned i=0, Offset=0;i<RetVals;i++) {
LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, Tys, Chain, LdLo, LdHi,
LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, LdLo, LdHi,
DAG.getConstant(LdOffset + Offset, MVT::i8),
InFlag);
@ -961,7 +962,7 @@ PIC16TargetLowering::LowerCallReturn(SDValue Op, SDValue Chain,
// To return use MERGE_VALUES
ResultVals.push_back(Chain);
SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size());
SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
return Res;
}

42
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1262,7 +1262,7 @@ SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
SDValue Ops[] =
{ CallResult.first, CallResult.second };
return DAG.getMergeValues(Ops, 2);
return DAG.getMergeValues(Ops, 2, dl);
}
SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
@ -2999,6 +2999,7 @@ SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
unsigned BitWidth = VT.getSizeInBits();
DebugLoc dl = Op.getDebugLoc();
assert(Op.getNumOperands() == 3 &&
VT == Op.getOperand(1).getValueType() &&
"Unexpected SHL!");
@ -3010,22 +3011,23 @@ SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
SDValue Amt = Op.getOperand(2);
MVT AmtVT = Amt.getValueType();
SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
DAG.getConstant(BitWidth, AmtVT), Amt);
SDValue Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt);
SDValue Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1);
SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
DAG.getConstant(-BitWidth, AmtVT));
SDValue Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5);
SDValue OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
SDValue OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt);
SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
SDValue OutOps[] = { OutLo, OutHi };
return DAG.getMergeValues(OutOps, 2);
return DAG.getMergeValues(OutOps, 2, dl);
}
SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
unsigned BitWidth = VT.getSizeInBits();
assert(Op.getNumOperands() == 3 &&
VT == Op.getOperand(1).getValueType() &&
@ -3038,18 +3040,18 @@ SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
SDValue Amt = Op.getOperand(2);
MVT AmtVT = Amt.getValueType();
SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
DAG.getConstant(BitWidth, AmtVT), Amt);
SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
DAG.getConstant(-BitWidth, AmtVT));
SDValue Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5);
SDValue OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
SDValue OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt);
SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
SDValue OutOps[] = { OutLo, OutHi };
return DAG.getMergeValues(OutOps, 2);
return DAG.getMergeValues(OutOps, 2, dl);
}
SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
@ -3078,7 +3080,7 @@ SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
Tmp4, Tmp6, ISD::SETLE);
SDValue OutOps[] = { OutLo, OutHi };
return DAG.getMergeValues(OutOps, 2);
return DAG.getMergeValues(OutOps, 2, dl);
}
//===----------------------------------------------------------------------===//