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d9d01917ee
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7aaa0aa7a7
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@ -61,8 +61,8 @@ class VectorLegalizer {
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// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
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// SINT_TO_FLOAT and SHR on vectors isn't legal.
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SDValue ExpandUINT_TO_FLOAT(SDValue Op);
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// Implement vselect in terms of XOR, AND,OR when blend is not supported
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// by the target.
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// Implement vselect in terms of XOR, AND, OR when blend is not supported
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// by the target.
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SDValue ExpandVSELECT(SDValue Op);
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SDValue ExpandFNEG(SDValue Op);
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// Implements vector promotion; this is essentially just bitcasting the
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@ -277,9 +277,8 @@ SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
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// AND,OR,XOR, we will have to scalarize the op.
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if (!TLI.isOperationLegalOrCustom(ISD::AND, VT) ||
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!TLI.isOperationLegalOrCustom(ISD::XOR, VT) ||
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!TLI.isOperationLegalOrCustom(ISD::OR, VT)) {
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return DAG.UnrollVectorOp(Op.getNode());
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}
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!TLI.isOperationLegalOrCustom(ISD::OR, VT))
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return DAG.UnrollVectorOp(Op.getNode());
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assert(VT.getSizeInBits() == OVT.getSizeInBits() && "Invalid mask size");
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// Bitcast the operands to be the same type as the mask.
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