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Allow vector integer constants to be created with 

SelectionDAG::getConstant, in the same way as vector floating-point
constants. This allows the legalize expansion code for @llvm.ctpop and
friends to be usable with vector types.

llvm-svn: 44954
This commit is contained in:
Dan Gohman 2007-12-12 22:21:26 +00:00
parent 9b7632eef8
commit 7a7742c2fe
3 changed files with 46 additions and 9 deletions
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31
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -687,22 +687,35 @@ SDOperand SelectionDAG::getString(const std::string &Val) {
SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT, bool isT) { SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT, bool isT) {
assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); assert(MVT::isInteger(VT) && "Cannot create FP integer constant!");
assert(!MVT::isVector(VT) && "Cannot create Vector ConstantSDNodes!");
MVT::ValueType EltVT =
MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT;
// Mask out any bits that are not valid for this constant. // Mask out any bits that are not valid for this constant.
Val &= MVT::getIntVTBitMask(VT); Val &= MVT::getIntVTBitMask(EltVT);
unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
FoldingSetNodeID ID; FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);
ID.AddInteger(Val); ID.AddInteger(Val);
void *IP = 0; void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) SDNode *N = NULL;
return SDOperand(E, 0); if ((N = CSEMap.FindNodeOrInsertPos(ID, IP)))
SDNode *N = new ConstantSDNode(isT, Val, VT); if (!MVT::isVector(VT))
CSEMap.InsertNode(N, IP); return SDOperand(N, 0);
AllNodes.push_back(N); if (!N) {
return SDOperand(N, 0); N = new ConstantSDNode(isT, Val, EltVT);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
}
SDOperand Result(N, 0);
if (MVT::isVector(VT)) {
SmallVector<SDOperand, 8> Ops;
Ops.assign(MVT::getVectorNumElements(VT), Result);
Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
}
return Result;
} }
SDOperand SelectionDAG::getConstantFP(const APFloat& V, MVT::ValueType VT, SDOperand SelectionDAG::getConstantFP(const APFloat& V, MVT::ValueType VT,

6
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -483,6 +483,12 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand); setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand); setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand); setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::SHL, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::SRA, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::SRL, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::ROTL, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::ROTR, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::BSWAP, (MVT::ValueType)VT, Expand);
} }
if (Subtarget->hasMMX()) { if (Subtarget->hasMMX()) {

18
llvm/test/CodeGen/X86/vec_ctbits.ll Normal file
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@ -0,0 +1,18 @@
; RUN: llvm-as < %s | llc -march=x86-64
declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>)
declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>)
declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
define <2 x i64> @footz(<2 x i64> %a) {
%c = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a)
ret <2 x i64> %c
}
define <2 x i64> @foolz(<2 x i64> %a) {
%c = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a)
ret <2 x i64> %c
}
define <2 x i64> @foopop(<2 x i64> %a) {
%c = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)
ret <2 x i64> %c
}