[MLIR][SPIRVToLLVM] Implementation of spv.BitFieldSExtract and spv.BitFieldUExtract patterns
This patch adds conversion patterns for `spv.BitFieldSExtract` and `spv.BitFieldUExtract`. As in the patch for `spv.BitFieldInsert`, `offset` and `count` have to be broadcasted in vector case and casted to match the type of the base. Reviewed By: antiagainst Differential Revision: https://reviews.llvm.org/D82640
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@ -119,7 +119,7 @@ static Value optionallyTruncateOrExtend(Location loc, Value value, Type dstType,
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return value;
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}
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/// Broadcasts the value to vector with `numElements` number of elements
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/// Broadcasts the value to vector with `numElements` number of elements.
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static Value broadcast(Location loc, Value toBroadcast, unsigned numElements,
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LLVMTypeConverter &typeConverter,
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ConversionPatternRewriter &rewriter) {
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@ -136,6 +136,35 @@ static Value broadcast(Location loc, Value toBroadcast, unsigned numElements,
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return broadcasted;
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}
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/// Broadcasts the value. If `srcType` is a scalar, the value remains unchanged.
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static Value optionallyBroadcast(Location loc, Value value, Type srcType,
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LLVMTypeConverter &typeConverter,
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ConversionPatternRewriter &rewriter) {
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if (auto vectorType = srcType.dyn_cast<VectorType>()) {
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unsigned numElements = vectorType.getNumElements();
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return broadcast(loc, value, numElements, typeConverter, rewriter);
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}
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return value;
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}
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/// Utility function for bitfiled ops: `BitFieldInsert`, `BitFieldSExtract` and
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/// `BitFieldUExtract`.
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/// Broadcast `Offset` and `Count` to match the type of `Base`. If `Base` is of
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/// a vector type, construct a vector that has:
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/// - same number of elements as `Base`
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/// - each element has the type that is the same as the type of `Offset` or
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/// `Count`
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/// - each element has the same value as `Offset` or `Count`
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/// Then cast `Offset` and `Count` if their bit width is different
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/// from `Base` bit width.
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static Value processCountOrOffset(Location loc, Value value, Type srcType,
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Type dstType, LLVMTypeConverter &converter,
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ConversionPatternRewriter &rewriter) {
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Value broadcasted =
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optionallyBroadcast(loc, value, srcType, converter, rewriter);
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return optionallyTruncateOrExtend(loc, broadcasted, dstType, rewriter);
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}
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//===----------------------------------------------------------------------===//
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// Operation conversion
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//===----------------------------------------------------------------------===//
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@ -156,41 +185,20 @@ public:
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return failure();
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Location loc = op.getLoc();
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// Broadcast `Offset` and `Count` to match the type of `Base` and `Insert`.
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// If `Base` is of a vector type, construct a vector that has:
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// - same number of elements as `Base`
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// - each element has the type that is the same as the type of `Offset` or
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// `Count`
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// - each element has the same value as `Offset` or `Count`
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Value offset;
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Value count;
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if (auto vectorType = srcType.dyn_cast<VectorType>()) {
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unsigned numElements = vectorType.getNumElements();
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offset =
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broadcast(loc, op.offset(), numElements, typeConverter, rewriter);
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count = broadcast(loc, op.count(), numElements, typeConverter, rewriter);
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} else {
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offset = op.offset();
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count = op.count();
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}
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// Create a mask with all bits set of the same type as `srcType`
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Value minusOne = createConstantAllBitsSet(loc, srcType, dstType, rewriter);
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// Need to cast `Offset` and `Count` if their bit width is different
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// from `Base` bit width.
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Value optionallyCastedCount =
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optionallyTruncateOrExtend(loc, count, dstType, rewriter);
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Value optionallyCastedOffset =
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optionallyTruncateOrExtend(loc, offset, dstType, rewriter);
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// Process `Offset` and `Count`: broadcast and extend/truncate if needed.
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Value offset = processCountOrOffset(loc, op.offset(), srcType, dstType,
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typeConverter, rewriter);
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Value count = processCountOrOffset(loc, op.count(), srcType, dstType,
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typeConverter, rewriter);
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// Create a mask with bits set outside [Offset, Offset + Count - 1].
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Value maskShiftedByCount = rewriter.create<LLVM::ShlOp>(
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loc, dstType, minusOne, optionallyCastedCount);
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Value minusOne = createConstantAllBitsSet(loc, srcType, dstType, rewriter);
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Value maskShiftedByCount =
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rewriter.create<LLVM::ShlOp>(loc, dstType, minusOne, count);
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Value negated = rewriter.create<LLVM::XOrOp>(loc, dstType,
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maskShiftedByCount, minusOne);
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Value maskShiftedByCountAndOffset = rewriter.create<LLVM::ShlOp>(
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loc, dstType, negated, optionallyCastedOffset);
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Value maskShiftedByCountAndOffset =
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rewriter.create<LLVM::ShlOp>(loc, dstType, negated, offset);
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Value mask = rewriter.create<LLVM::XOrOp>(
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loc, dstType, maskShiftedByCountAndOffset, minusOne);
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@ -198,8 +206,8 @@ public:
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// [Offset, Offset + Count - 1]. Then `or` with shifted `Insert`.
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Value baseAndMask =
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rewriter.create<LLVM::AndOp>(loc, dstType, op.base(), mask);
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Value insertShiftedByOffset = rewriter.create<LLVM::ShlOp>(
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loc, dstType, op.insert(), optionallyCastedOffset);
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Value insertShiftedByOffset =
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rewriter.create<LLVM::ShlOp>(loc, dstType, op.insert(), offset);
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rewriter.replaceOpWithNewOp<LLVM::OrOp>(op, dstType, baseAndMask,
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insertShiftedByOffset);
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return success();
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@ -252,6 +260,94 @@ public:
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}
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};
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class BitFieldSExtractPattern
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: public SPIRVToLLVMConversion<spirv::BitFieldSExtractOp> {
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public:
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using SPIRVToLLVMConversion<spirv::BitFieldSExtractOp>::SPIRVToLLVMConversion;
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LogicalResult
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matchAndRewrite(spirv::BitFieldSExtractOp op, ArrayRef<Value> operands,
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ConversionPatternRewriter &rewriter) const override {
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auto srcType = op.getType();
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auto dstType = this->typeConverter.convertType(srcType);
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if (!dstType)
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return failure();
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Location loc = op.getLoc();
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// Process `Offset` and `Count`: broadcast and extend/truncate if needed.
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Value offset = processCountOrOffset(loc, op.offset(), srcType, dstType,
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typeConverter, rewriter);
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Value count = processCountOrOffset(loc, op.count(), srcType, dstType,
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typeConverter, rewriter);
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// Create a constant that holds the size of the `Base`.
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IntegerType integerType;
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if (auto vecType = srcType.dyn_cast<VectorType>())
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integerType = vecType.getElementType().cast<IntegerType>();
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else
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integerType = srcType.cast<IntegerType>();
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auto baseSize = rewriter.getIntegerAttr(integerType, getBitWidth(srcType));
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Value size =
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srcType.isa<VectorType>()
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? rewriter.create<LLVM::ConstantOp>(
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loc, dstType,
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SplatElementsAttr::get(srcType.cast<ShapedType>(), baseSize))
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: rewriter.create<LLVM::ConstantOp>(loc, dstType, baseSize);
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// Shift `Base` left by [sizeof(Base) - (Count + Offset)], so that the bit
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// at Offset + Count - 1 is the most significant bit now.
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Value countPlusOffset =
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rewriter.create<LLVM::AddOp>(loc, dstType, count, offset);
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Value amountToShiftLeft =
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rewriter.create<LLVM::SubOp>(loc, dstType, size, countPlusOffset);
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Value baseShiftedLeft = rewriter.create<LLVM::ShlOp>(
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loc, dstType, op.base(), amountToShiftLeft);
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// Shift the result right, filling the bits with the sign bit.
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Value amountToShiftRight =
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rewriter.create<LLVM::AddOp>(loc, dstType, offset, amountToShiftLeft);
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rewriter.replaceOpWithNewOp<LLVM::AShrOp>(op, dstType, baseShiftedLeft,
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amountToShiftRight);
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return success();
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}
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};
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class BitFieldUExtractPattern
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: public SPIRVToLLVMConversion<spirv::BitFieldUExtractOp> {
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public:
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using SPIRVToLLVMConversion<spirv::BitFieldUExtractOp>::SPIRVToLLVMConversion;
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LogicalResult
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matchAndRewrite(spirv::BitFieldUExtractOp op, ArrayRef<Value> operands,
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ConversionPatternRewriter &rewriter) const override {
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auto srcType = op.getType();
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auto dstType = this->typeConverter.convertType(srcType);
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if (!dstType)
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return failure();
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Location loc = op.getLoc();
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// Process `Offset` and `Count`: broadcast and extend/truncate if needed.
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Value offset = processCountOrOffset(loc, op.offset(), srcType, dstType,
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typeConverter, rewriter);
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Value count = processCountOrOffset(loc, op.count(), srcType, dstType,
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typeConverter, rewriter);
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// Create a mask with bits set at [0, Count - 1].
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Value minusOne = createConstantAllBitsSet(loc, srcType, dstType, rewriter);
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Value maskShiftedByCount =
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rewriter.create<LLVM::ShlOp>(loc, dstType, minusOne, count);
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Value mask = rewriter.create<LLVM::XOrOp>(loc, dstType, maskShiftedByCount,
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minusOne);
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// Shift `Base` by `Offset` and apply the mask on it.
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Value shiftedBase =
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rewriter.create<LLVM::LShrOp>(loc, dstType, op.base(), offset);
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rewriter.replaceOpWithNewOp<LLVM::AndOp>(op, dstType, shiftedBase, mask);
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return success();
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}
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};
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/// Converts SPIR-V operations that have straightforward LLVM equivalent
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/// into LLVM dialect operations.
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template <typename SPIRVOp, typename LLVMOp>
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@ -586,7 +682,7 @@ void mlir::populateSPIRVToLLVMConversionPatterns(
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DirectConversionPattern<spirv::UModOp, LLVM::URemOp>,
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// Bitwise ops
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BitFieldInsertPattern,
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BitFieldInsertPattern, BitFieldUExtractPattern, BitFieldSExtractPattern,
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DirectConversionPattern<spirv::BitCountOp, LLVM::CtPopOp>,
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DirectConversionPattern<spirv::BitReverseOp, LLVM::BitReverseOp>,
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DirectConversionPattern<spirv::BitwiseAndOp, LLVM::AndOp>,
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@ -54,9 +54,9 @@ func @bitfield_insert_scalar_same_bit_width(%base: i32, %insert: i32, %offset: i
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// CHECK-LABEL: func @bitfield_insert_scalar_smaller_bit_width
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// CHECK-SAME: %[[BASE:.*]]: !llvm.i64, %[[INSERT:.*]]: !llvm.i64, %[[OFFSET:.*]]: !llvm.i8, %[[COUNT:.*]]: !llvm.i8
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func @bitfield_insert_scalar_smaller_bit_width(%base: i64, %insert: i64, %offset: i8, %count: i8) {
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// CHECK: %[[MINUS_ONE:.*]] = llvm.mlir.constant(-1 : i64) : !llvm.i64
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// CHECK: %[[EXT_COUNT:.*]] = llvm.zext %[[COUNT]] : !llvm.i8 to !llvm.i64
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// CHECK: %[[EXT_OFFSET:.*]] = llvm.zext %[[OFFSET]] : !llvm.i8 to !llvm.i64
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// CHECK: %[[EXT_COUNT:.*]] = llvm.zext %[[COUNT]] : !llvm.i8 to !llvm.i64
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// CHECK: %[[MINUS_ONE:.*]] = llvm.mlir.constant(-1 : i64) : !llvm.i64
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// CHECK: %[[T0:.*]] = llvm.shl %[[MINUS_ONE]], %[[EXT_COUNT]] : !llvm.i64
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// CHECK: %[[T1:.*]] = llvm.xor %[[T0]], %[[MINUS_ONE]] : !llvm.i64
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// CHECK: %[[T2:.*]] = llvm.shl %[[T1]], %[[EXT_OFFSET]] : !llvm.i64
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@ -71,9 +71,9 @@ func @bitfield_insert_scalar_smaller_bit_width(%base: i64, %insert: i64, %offset
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// CHECK-LABEL: func @bitfield_insert_scalar_greater_bit_width
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// CHECK-SAME: %[[BASE:.*]]: !llvm.i16, %[[INSERT:.*]]: !llvm.i16, %[[OFFSET:.*]]: !llvm.i32, %[[COUNT:.*]]: !llvm.i64
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func @bitfield_insert_scalar_greater_bit_width(%base: i16, %insert: i16, %offset: i32, %count: i64) {
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// CHECK: %[[MINUS_ONE:.*]] = llvm.mlir.constant(-1 : i16) : !llvm.i16
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// CHECK: %[[TRUNC_COUNT:.*]] = llvm.trunc %[[COUNT]] : !llvm.i64 to !llvm.i16
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// CHECK: %[[TRUNC_OFFSET:.*]] = llvm.trunc %[[OFFSET]] : !llvm.i32 to !llvm.i16
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// CHECK: %[[TRUNC_COUNT:.*]] = llvm.trunc %[[COUNT]] : !llvm.i64 to !llvm.i16
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// CHECK: %[[MINUS_ONE:.*]] = llvm.mlir.constant(-1 : i16) : !llvm.i16
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// CHECK: %[[T0:.*]] = llvm.shl %[[MINUS_ONE]], %[[TRUNC_COUNT]] : !llvm.i16
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// CHECK: %[[T1:.*]] = llvm.xor %[[T0]], %[[MINUS_ONE]] : !llvm.i16
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// CHECK: %[[T2:.*]] = llvm.shl %[[T1]], %[[TRUNC_OFFSET]] : !llvm.i16
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@ -110,6 +110,141 @@ func @bitfield_insert_vector(%base: vector<2xi32>, %insert: vector<2xi32>, %offs
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return
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}
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//===----------------------------------------------------------------------===//
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// spv.BitFieldSExtract
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//===----------------------------------------------------------------------===//
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// CHECK-LABEL: func @bitfield_sextract_scalar_same_bit_width
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// CHECK-SAME: %[[BASE:.*]]: !llvm.i64, %[[OFFSET:.*]]: !llvm.i64, %[[COUNT:.*]]: !llvm.i64
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func @bitfield_sextract_scalar_same_bit_width(%base: i64, %offset: i64, %count: i64) {
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// CHECK: %[[SIZE:.]] = llvm.mlir.constant(64 : i64) : !llvm.i64
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// CHECK: %[[T0:.*]] = llvm.add %[[COUNT]], %[[OFFSET]] : !llvm.i64
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// CHECK: %[[T1:.*]] = llvm.sub %[[SIZE]], %[[T0]] : !llvm.i64
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// CHECK: %[[SHIFTED_LEFT:.*]] = llvm.shl %[[BASE]], %[[T1]] : !llvm.i64
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// CHECK: %[[T2:.*]] = llvm.add %[[OFFSET]], %[[T1]] : !llvm.i64
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// CHECK: %{{.*}} = llvm.ashr %[[SHIFTED_LEFT]], %[[T2]] : !llvm.i64
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%0 = spv.BitFieldSExtract %base, %offset, %count : i64, i64, i64
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return
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}
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// CHECK-LABEL: func @bitfield_sextract_scalar_smaller_bit_width
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// CHECK-SAME: %[[BASE:.*]]: !llvm.i32, %[[OFFSET:.*]]: !llvm.i8, %[[COUNT:.*]]: !llvm.i8
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func @bitfield_sextract_scalar_smaller_bit_width(%base: i32, %offset: i8, %count: i8) {
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// CHECK: %[[EXT_OFFSET:.*]] = llvm.zext %[[OFFSET]] : !llvm.i8 to !llvm.i32
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// CHECK: %[[EXT_COUNT:.*]] = llvm.zext %[[COUNT]] : !llvm.i8 to !llvm.i32
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// CHECK: %[[SIZE:.]] = llvm.mlir.constant(32 : i32) : !llvm.i32
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// CHECK: %[[T0:.*]] = llvm.add %[[EXT_COUNT]], %[[EXT_OFFSET]] : !llvm.i32
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// CHECK: %[[T1:.*]] = llvm.sub %[[SIZE]], %[[T0]] : !llvm.i32
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// CHECK: %[[SHIFTED_LEFT:.*]] = llvm.shl %[[BASE]], %[[T1]] : !llvm.i32
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// CHECK: %[[T2:.*]] = llvm.add %[[EXT_OFFSET]], %[[T1]] : !llvm.i32
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// CHECK: %{{.*}} = llvm.ashr %[[SHIFTED_LEFT]], %[[T2]] : !llvm.i32
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%0 = spv.BitFieldSExtract %base, %offset, %count : i32, i8, i8
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return
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}
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// CHECK-LABEL: func @bitfield_sextract_scalar_greater_bit_width
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// CHECK-SAME: %[[BASE:.*]]: !llvm.i32, %[[OFFSET:.*]]: !llvm.i64, %[[COUNT:.*]]: !llvm.i64
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func @bitfield_sextract_scalar_greater_bit_width(%base: i32, %offset: i64, %count: i64) {
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// CHECK: %[[TRUNC_OFFSET:.*]] = llvm.trunc %[[OFFSET]] : !llvm.i64 to !llvm.i32
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// CHECK: %[[TRUNC_COUNT:.*]] = llvm.trunc %[[COUNT]] : !llvm.i64 to !llvm.i32
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// CHECK: %[[SIZE:.]] = llvm.mlir.constant(32 : i32) : !llvm.i32
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// CHECK: %[[T0:.*]] = llvm.add %[[TRUNC_COUNT]], %[[TRUNC_OFFSET]] : !llvm.i32
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// CHECK: %[[T1:.*]] = llvm.sub %[[SIZE]], %[[T0]] : !llvm.i32
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// CHECK: %[[SHIFTED_LEFT:.*]] = llvm.shl %[[BASE]], %[[T1]] : !llvm.i32
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// CHECK: %[[T2:.*]] = llvm.add %[[TRUNC_OFFSET]], %[[T1]] : !llvm.i32
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// CHECK: %{{.*}} = llvm.ashr %[[SHIFTED_LEFT]], %[[T2]] : !llvm.i32
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%0 = spv.BitFieldSExtract %base, %offset, %count : i32, i64, i64
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return
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}
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// CHECK-LABEL: func @bitfield_sextract_vector
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// CHECK-SAME: %[[BASE:.*]]: !llvm<"<2 x i32>">, %[[OFFSET:.*]]: !llvm.i32, %[[COUNT:.*]]: !llvm.i32
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func @bitfield_sextract_vector(%base: vector<2xi32>, %offset: i32, %count: i32) {
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// CHECK: %[[OFFSET_V0:.*]] = llvm.mlir.undef : !llvm<"<2 x i32>">
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// CHECK: %[[ZERO:.*]] = llvm.mlir.constant(0 : i32) : !llvm.i32
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// CHECK: %[[OFFSET_V1:.*]] = llvm.insertelement %[[OFFSET]], %[[OFFSET_V0]][%[[ZERO]] : !llvm.i32] : !llvm<"<2 x i32>">
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// CHECK: %[[ONE:.*]] = llvm.mlir.constant(1 : i32) : !llvm.i32
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// CHECK: %[[OFFSET_V2:.*]] = llvm.insertelement %[[OFFSET]], %[[OFFSET_V1]][%[[ONE]] : !llvm.i32] : !llvm<"<2 x i32>">
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// CHECK: %[[COUNT_V0:.*]] = llvm.mlir.undef : !llvm<"<2 x i32>">
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// CHECK: %[[ZERO:.*]] = llvm.mlir.constant(0 : i32) : !llvm.i32
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// CHECK: %[[COUNT_V1:.*]] = llvm.insertelement %[[COUNT]], %[[COUNT_V0]][%[[ZERO]] : !llvm.i32] : !llvm<"<2 x i32>">
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// CHECK: %[[ONE:.*]] = llvm.mlir.constant(1 : i32) : !llvm.i32
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// CHECK: %[[COUNT_V2:.*]] = llvm.insertelement %[[COUNT]], %[[COUNT_V1]][%[[ONE]] : !llvm.i32] : !llvm<"<2 x i32>">
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// CHECK: %[[SIZE:.*]] = llvm.mlir.constant(dense<32> : vector<2xi32>) : !llvm<"<2 x i32>">
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// CHECK: %[[T0:.*]] = llvm.add %[[COUNT_V2]], %[[OFFSET_V2]] : !llvm<"<2 x i32>">
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// CHECK: %[[T1:.*]] = llvm.sub %[[SIZE]], %[[T0]] : !llvm<"<2 x i32>">
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// CHECK: %[[SHIFTED_LEFT:.*]] = llvm.shl %[[BASE]], %[[T1]] : !llvm<"<2 x i32>">
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// CHECK: %[[T2:.*]] = llvm.add %[[OFFSET_V2]], %[[T1]] : !llvm<"<2 x i32>">
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// CHECK: %{{.*}} = llvm.ashr %[[SHIFTED_LEFT]], %[[T2]] : !llvm<"<2 x i32>">
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%0 = spv.BitFieldSExtract %base, %offset, %count : vector<2xi32>, i32, i32
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return
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}
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//===----------------------------------------------------------------------===//
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// spv.BitFieldUExtract
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//===----------------------------------------------------------------------===//
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// CHECK-LABEL: func @bitfield_uextract_scalar_same_bit_width
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// CHECK-SAME: %[[BASE:.*]]: !llvm.i32, %[[OFFSET:.*]]: !llvm.i32, %[[COUNT:.*]]: !llvm.i32
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func @bitfield_uextract_scalar_same_bit_width(%base: i32, %offset: i32, %count: i32) {
|
||||
// CHECK: %[[MINUS_ONE:.*]] = llvm.mlir.constant(-1 : i32) : !llvm.i32
|
||||
// CHECK: %[[T0:.*]] = llvm.shl %[[MINUS_ONE]], %[[COUNT]] : !llvm.i32
|
||||
// CHECK: %[[MASK:.*]] = llvm.xor %[[T0]], %[[MINUS_ONE]] : !llvm.i32
|
||||
// CHECK: %[[SHIFTED_BASE:.*]] = llvm.lshr %[[BASE]], %[[OFFSET]] : !llvm.i32
|
||||
// CHECK: %{{.*}} = llvm.and %[[SHIFTED_BASE]], %[[MASK]] : !llvm.i32
|
||||
%0 = spv.BitFieldUExtract %base, %offset, %count : i32, i32, i32
|
||||
return
|
||||
}
|
||||
|
||||
// CHECK-LABEL: func @bitfield_uextract_scalar_smaller_bit_width
|
||||
// CHECK-SAME: %[[BASE:.*]]: !llvm.i32, %[[OFFSET:.*]]: !llvm.i16, %[[COUNT:.*]]: !llvm.i8
|
||||
func @bitfield_uextract_scalar_smaller_bit_width(%base: i32, %offset: i16, %count: i8) {
|
||||
// CHECK: %[[EXT_OFFSET:.*]] = llvm.zext %[[OFFSET]] : !llvm.i16 to !llvm.i32
|
||||
// CHECK: %[[EXT_COUNT:.*]] = llvm.zext %[[COUNT]] : !llvm.i8 to !llvm.i32
|
||||
// CHECK: %[[MINUS_ONE:.*]] = llvm.mlir.constant(-1 : i32) : !llvm.i32
|
||||
// CHECK: %[[T0:.*]] = llvm.shl %[[MINUS_ONE]], %[[EXT_COUNT]] : !llvm.i32
|
||||
// CHECK: %[[MASK:.*]] = llvm.xor %[[T0]], %[[MINUS_ONE]] : !llvm.i32
|
||||
// CHECK: %[[SHIFTED_BASE:.*]] = llvm.lshr %[[BASE]], %[[EXT_OFFSET]] : !llvm.i32
|
||||
// CHECK: %{{.*}} = llvm.and %[[SHIFTED_BASE]], %[[MASK]] : !llvm.i32
|
||||
%0 = spv.BitFieldUExtract %base, %offset, %count : i32, i16, i8
|
||||
return
|
||||
}
|
||||
|
||||
// CHECK-LABEL: func @bitfield_uextract_scalar_greater_bit_width
|
||||
// CHECK-SAME: %[[BASE:.*]]: !llvm.i8, %[[OFFSET:.*]]: !llvm.i16, %[[COUNT:.*]]: !llvm.i8
|
||||
func @bitfield_uextract_scalar_greater_bit_width(%base: i8, %offset: i16, %count: i8) {
|
||||
// CHECK: %[[TRUNC_OFFSET:.*]] = llvm.trunc %[[OFFSET]] : !llvm.i16 to !llvm.i8
|
||||
// CHECK: %[[MINUS_ONE:.*]] = llvm.mlir.constant(-1 : i8) : !llvm.i8
|
||||
// CHECK: %[[T0:.*]] = llvm.shl %[[MINUS_ONE]], %[[COUNT]] : !llvm.i8
|
||||
// CHECK: %[[MASK:.*]] = llvm.xor %[[T0]], %[[MINUS_ONE]] : !llvm.i8
|
||||
// CHECK: %[[SHIFTED_BASE:.*]] = llvm.lshr %[[BASE]], %[[TRUNC_OFFSET]] : !llvm.i8
|
||||
// CHECK: %{{.*}} = llvm.and %[[SHIFTED_BASE]], %[[MASK]] : !llvm.i8
|
||||
%0 = spv.BitFieldUExtract %base, %offset, %count : i8, i16, i8
|
||||
return
|
||||
}
|
||||
|
||||
// CHECK-LABEL: func @bitfield_uextract_vector
|
||||
// CHECK-SAME: %[[BASE:.*]]: !llvm<"<2 x i32>">, %[[OFFSET:.*]]: !llvm.i32, %[[COUNT:.*]]: !llvm.i32
|
||||
func @bitfield_uextract_vector(%base: vector<2xi32>, %offset: i32, %count: i32) {
|
||||
// CHECK: %[[OFFSET_V0:.*]] = llvm.mlir.undef : !llvm<"<2 x i32>">
|
||||
// CHECK: %[[ZERO:.*]] = llvm.mlir.constant(0 : i32) : !llvm.i32
|
||||
// CHECK: %[[OFFSET_V1:.*]] = llvm.insertelement %[[OFFSET]], %[[OFFSET_V0]][%[[ZERO]] : !llvm.i32] : !llvm<"<2 x i32>">
|
||||
// CHECK: %[[ONE:.*]] = llvm.mlir.constant(1 : i32) : !llvm.i32
|
||||
// CHECK: %[[OFFSET_V2:.*]] = llvm.insertelement %[[OFFSET]], %[[OFFSET_V1]][%[[ONE]] : !llvm.i32] : !llvm<"<2 x i32>">
|
||||
// CHECK: %[[COUNT_V0:.*]] = llvm.mlir.undef : !llvm<"<2 x i32>">
|
||||
// CHECK: %[[ZERO:.*]] = llvm.mlir.constant(0 : i32) : !llvm.i32
|
||||
// CHECK: %[[COUNT_V1:.*]] = llvm.insertelement %[[COUNT]], %[[COUNT_V0]][%[[ZERO]] : !llvm.i32] : !llvm<"<2 x i32>">
|
||||
// CHECK: %[[ONE:.*]] = llvm.mlir.constant(1 : i32) : !llvm.i32
|
||||
// CHECK: %[[COUNT_V2:.*]] = llvm.insertelement %[[COUNT]], %[[COUNT_V1]][%[[ONE]] : !llvm.i32] : !llvm<"<2 x i32>">
|
||||
// CHECK: %[[MINUS_ONE:.*]] = llvm.mlir.constant(dense<-1> : vector<2xi32>) : !llvm<"<2 x i32>">
|
||||
// CHECK: %[[T0:.*]] = llvm.shl %[[MINUS_ONE]], %[[COUNT_V2]] : !llvm<"<2 x i32>">
|
||||
// CHECK: %[[MASK:.*]] = llvm.xor %[[T0]], %[[MINUS_ONE]] : !llvm<"<2 x i32>">
|
||||
// CHECK: %[[SHIFTED_BASE:.*]] = llvm.lshr %[[BASE]], %[[OFFSET_V2]] : !llvm<"<2 x i32>">
|
||||
// CHECK: %{{.*}} = llvm.and %[[SHIFTED_BASE]], %[[MASK]] : !llvm<"<2 x i32>">
|
||||
%0 = spv.BitFieldUExtract %base, %offset, %count : vector<2xi32>, i32, i32
|
||||
return
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// spv.BitwiseAnd
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
Loading…
Reference in New Issue