[AArch64][GlobalISel] Add the Localizer pass for the O0 pipeline
This should fix most of the issue we have right now with constants being spilled all over the place. llvm-svn: 304052
This commit is contained in:
Quentin Colombet
parent
bece442bd8
commit
7a43eddf28
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@ -10,10 +10,10 @@
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64TargetMachine.h"
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#include "AArch64.h"
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#include "AArch64MacroFusion.h"
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#include "AArch64Subtarget.h"
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#include "AArch64TargetMachine.h"
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#include "AArch64TargetObjectFile.h"
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#include "AArch64TargetTransformInfo.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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@ -23,6 +23,7 @@
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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#include "llvm/CodeGen/GlobalISel/Legalizer.h"
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#include "llvm/CodeGen/GlobalISel/Localizer.h"
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#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/CodeGen/Passes.h"
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@ -295,6 +296,7 @@ public:
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bool addIRTranslator() override;
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bool addLegalizeMachineIR() override;
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bool addRegBankSelect() override;
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void addPreGlobalInstructionSelect() override;
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bool addGlobalInstructionSelect() override;
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#endif
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bool addILPOpts() override;
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@ -404,6 +406,12 @@ bool AArch64PassConfig::addRegBankSelect() {
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return false;
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}
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void AArch64PassConfig::addPreGlobalInstructionSelect() {
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// Workaround the deficiency of the fast register allocator.
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if (TM->getOptLevel() == CodeGenOpt::None)
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addPass(new Localizer());
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}
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bool AArch64PassConfig::addGlobalInstructionSelect() {
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addPass(new InstructionSelect());
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return false;
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@ -43,7 +43,7 @@ define [1 x double] @constant() {
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; The key problem here is that we may fail to create an MBB referenced by a
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; PHI. If so, we cannot complete the G_PHI and mustn't try or bad things
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; happen.
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: G_STORE %vreg4, %vreg2; mem:ST4[%addr] GPR:%vreg4,%vreg2 (in function: pending_phis)
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: G_STORE %vreg5, %vreg2; mem:ST4[%addr] GPR:%vreg5,%vreg2 (in function: pending_phis)
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for pending_phis
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; FALLBACK-WITH-REPORT-OUT-LABEL: pending_phis:
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define i32 @pending_phis(i1 %tst, i32 %val, i32* %addr) {
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@ -1,10 +1,10 @@
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; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: -O0 -aarch64-enable-global-isel-at-O=0 \
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; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix NOFALLBACK
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; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix ENABLED-O0 --check-prefix NOFALLBACK
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; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: -O0 -aarch64-enable-global-isel-at-O=0 -global-isel-abort=2 \
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; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix FALLBACK
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; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix ENABLED-O0 --check-prefix FALLBACK
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; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: -global-isel \
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@ -32,6 +32,7 @@
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; ENABLED: IRTranslator
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; ENABLED-NEXT: Legalizer
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; ENABLED-NEXT: RegBankSelect
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; ENABLED-O0-NEXT: Localizer
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; ENABLED-NEXT: InstructionSelect
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; ENABLED-NEXT: ResetMachineFunction
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@ -0,0 +1,96 @@
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# RUN: llc -O0 -mtriple aarch64-apple-ios %s -global-isel -start-after regbankselect \
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# RUN: -stop-before instruction-select -o - | FileCheck --check-prefix=CHECK --check-prefix=OPTNONE %s
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# RUN: llc -mtriple aarch64-apple-ios %s -global-isel -start-after regbankselect \
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# RUN: -stop-before instruction-select -o - | FileCheck --check-prefix=CHECK --check-prefix=OPT %s
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#
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# Check that we are only running the localizer at O0 and that it runs
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# between the regbankselect pass and the instruction-select.
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# Moreover, check that it does what we expect.
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-apple-ios"
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define float @foo(float %arg, i1 %cond) {
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br i1 %cond, label %true, label %false
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true: ; preds = %0
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br label %end
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false: ; preds = %0
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br label %end
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end: ; preds = %false, %true
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%val = phi float [ 1.000000e+00, %true ], [ 2.000000e+00, %false ]
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%res = fadd float %arg, %val
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ret float %res
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}
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...
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---
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# CHECK-LABEL: name: foo
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name: foo
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: fpr }
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# CHECK-NEXT: - { id: 1, class: gpr }
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# CHECK-NEXT: - { id: 2, class: fpr }
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# CHECK-NEXT: - { id: 3, class: fpr }
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# CHECK-NEXT: - { id: 4, class: fpr }
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# CHECK-NEXT: - { id: 5, class: fpr }
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# The localizer will create two new values to materialize the constants.
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# OPTNONE-NEXT: - { id: 6, class: fpr }
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# OPTNONE-NEXT: - { id: 7, class: fpr }
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- { id: 0, class: fpr }
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- { id: 1, class: gpr }
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- { id: 2, class: fpr }
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- { id: 3, class: fpr }
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- { id: 4, class: fpr }
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- { id: 5, class: fpr }
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# First block remains untouched
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# CHECK: body
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# CHECK: %4(s32) = G_FCONSTANT float 1.000000e+00
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# CHECK: %5(s32) = G_FCONSTANT float 2.000000e+00
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# Second block will get the constant 1.0 when the localizer is enabled.
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# CHECK: bb.1.true:
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# OPT-NOT: G_FCONSTANT
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# OPTNONE: [[FONE:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
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# CHECK: G_BR %bb.3.end
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# Thrid block will get the constant 2.0 when the localizer is enabled.
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# CHECK: bb.2.false:
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# OPT-NOT: G_FCONSTANT
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# OPTNONE: [[FTWO:%[0-9]+]](s32) = G_FCONSTANT float 2.000000e+00
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# CHECK: bb.3.end
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# OPTNONE: %2(s32) = PHI [[FONE]](s32), %bb.1.true, [[FTWO]](s32), %bb.2.false
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# OPT: %2(s32) = PHI %4(s32), %bb.1.true, %5(s32), %bb.2.false
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# CHECK-NEXT: G_FADD %0, %2
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body: |
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bb.0 (%ir-block.0):
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liveins: %s0, %w0
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%0(s32) = COPY %s0
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%1(s1) = COPY %w0
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%4(s32) = G_FCONSTANT float 1.000000e+00
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%5(s32) = G_FCONSTANT float 2.000000e+00
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G_BRCOND %1(s1), %bb.1.true
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G_BR %bb.2.false
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bb.1.true:
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G_BR %bb.3.end
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bb.2.false:
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bb.3.end:
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%2(s32) = PHI %4(s32), %bb.1.true, %5(s32), %bb.2.false
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%3(s32) = G_FADD %0, %2
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%s0 = COPY %3(s32)
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RET_ReallyLR implicit %s0
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...
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