parent
7c76278242
commit
79f5ebc7b9
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@ -808,11 +808,12 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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SDNode *Node = N.Val;
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SDNode *Node = N.Val;
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MVT::ValueType DestType = N.getValueType();
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MVT::ValueType DestType = N.getValueType();
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if (Node->getOpcode() == ISD::CopyFromReg &&
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if (Node->getOpcode() == ISD::CopyFromReg) {
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(MRegisterInfo::isVirtualRegister(cast<RegSDNode>(Node)->getReg()) ||
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unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
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cast<RegSDNode>(Node)->getReg() == PPC::R1))
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// Just use the specified register as our input.
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// Just use the specified register as our input.
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return cast<RegSDNode>(Node)->getReg();
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if (MRegisterInfo::isVirtualRegister(Reg) || Reg == PPC::R1)
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return Reg;
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}
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unsigned &Reg = ExprMap[N];
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unsigned &Reg = ExprMap[N];
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if (Reg) return Reg;
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if (Reg) return Reg;
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@ -1085,7 +1086,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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DestType = N.getValue(0).getValueType();
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DestType = N.getValue(0).getValueType();
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if (Result == 1)
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if (Result == 1)
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Result = ExprMap[N.getValue(0)] = MakeReg(DestType);
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Result = ExprMap[N.getValue(0)] = MakeReg(DestType);
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Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
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Tmp1 = dyn_cast<RegisterSDNode>(Node->getOperand(1))->getReg();
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if (MVT::isInteger(DestType))
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if (MVT::isInteger(DestType))
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BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
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BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
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else
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else
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@ -1877,12 +1878,12 @@ void ISel::Select(SDOperand N) {
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return;
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return;
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case ISD::CopyToReg:
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case ISD::CopyToReg:
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Select(N.getOperand(0));
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Select(N.getOperand(0));
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Tmp1 = SelectExpr(N.getOperand(1));
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Tmp1 = SelectExpr(N.getOperand(2));
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Tmp2 = cast<RegSDNode>(N)->getReg();
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Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
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if (Tmp1 != Tmp2) {
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if (Tmp1 != Tmp2) {
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if (N.getOperand(1).getValueType() == MVT::f64 ||
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if (N.getOperand(2).getValueType() == MVT::f64 ||
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N.getOperand(1).getValueType() == MVT::f32)
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N.getOperand(2).getValueType() == MVT::f32)
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BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
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BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
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else
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else
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BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
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BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
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@ -1890,7 +1891,8 @@ void ISel::Select(SDOperand N) {
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return;
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return;
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case ISD::ImplicitDef:
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case ISD::ImplicitDef:
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Select(N.getOperand(0));
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Select(N.getOperand(0));
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BuildMI(BB, PPC::IMPLICIT_DEF, 0, cast<RegSDNode>(N)->getReg());
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BuildMI(BB, PPC::IMPLICIT_DEF, 0,
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cast<RegisterSDNode>(N.getOperand(1))->getReg());
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return;
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return;
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case ISD::RET:
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case ISD::RET:
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switch (N.getNumOperands()) {
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switch (N.getNumOperands()) {
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@ -128,8 +128,8 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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if (!ArgLive) break;
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if (!ArgLive) break;
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if (GPR_remaining > 0) {
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if (GPR_remaining > 0) {
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MF.addLiveIn(GPR[GPR_idx]);
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MF.addLiveIn(GPR[GPR_idx]);
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argt = newroot = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
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argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
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DAG.getRoot());
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GPR[GPR_idx], MVT::i32);
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if (ObjectVT != MVT::i32)
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if (ObjectVT != MVT::i32)
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argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
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argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
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} else {
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} else {
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@ -141,14 +141,14 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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if (GPR_remaining > 0) {
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if (GPR_remaining > 0) {
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SDOperand argHi, argLo;
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SDOperand argHi, argLo;
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MF.addLiveIn(GPR[GPR_idx]);
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MF.addLiveIn(GPR[GPR_idx]);
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argHi = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
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argHi = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
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// If we have two or more remaining argument registers, then both halves
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// If we have two or more remaining argument registers, then both halves
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// of the i64 can be sourced from there. Otherwise, the lower half will
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// of the i64 can be sourced from there. Otherwise, the lower half will
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// have to come off the stack. This can happen when an i64 is preceded
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// have to come off the stack. This can happen when an i64 is preceded
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// by 28 bytes of arguments.
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// by 28 bytes of arguments.
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if (GPR_remaining > 1) {
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if (GPR_remaining > 1) {
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MF.addLiveIn(GPR[GPR_idx+1]);
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MF.addLiveIn(GPR[GPR_idx+1]);
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argLo = DAG.getCopyFromReg(GPR[GPR_idx+1], MVT::i32, argHi);
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argLo = DAG.getCopyFromReg(argHi, GPR[GPR_idx+1], MVT::i32);
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} else {
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} else {
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int FI = MFI->CreateFixedObject(4, ArgOffset+4);
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int FI = MFI->CreateFixedObject(4, ArgOffset+4);
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
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@ -168,8 +168,8 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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if (!ArgLive) break;
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if (!ArgLive) break;
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if (FPR_remaining > 0) {
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if (FPR_remaining > 0) {
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MF.addLiveIn(FPR[FPR_idx]);
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MF.addLiveIn(FPR[FPR_idx]);
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argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
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argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
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DAG.getRoot());
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FPR[FPR_idx], ObjectVT);
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--FPR_remaining;
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--FPR_remaining;
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++FPR_idx;
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++FPR_idx;
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} else {
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} else {
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@ -217,7 +217,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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std::vector<SDOperand> MemOps;
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std::vector<SDOperand> MemOps;
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for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
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for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
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MF.addLiveIn(GPR[GPR_idx]);
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MF.addLiveIn(GPR[GPR_idx]);
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SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
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SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
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SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
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SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
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Val, FIN, DAG.getSrcValue(NULL));
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Val, FIN, DAG.getSrcValue(NULL));
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MemOps.push_back(Store);
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MemOps.push_back(Store);
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@ -298,8 +298,8 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
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// Set up a copy of the stack pointer for use loading and storing any
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// Set up a copy of the stack pointer for use loading and storing any
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// arguments that may not fit in the registers available for argument
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// arguments that may not fit in the registers available for argument
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// passing.
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// passing.
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SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
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SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
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DAG.getEntryNode());
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PPC::R1, MVT::i32);
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// Figure out which arguments are going to go in registers, and which in
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// Figure out which arguments are going to go in registers, and which in
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// memory. Also, if this is a vararg function, floating point operations
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// memory. Also, if this is a vararg function, floating point operations
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