AMDGPU: Unify MOVRELSOffset and MOVRELDOffset
Summary: Previously, constant index insertelements would be turned into SI_INDIRECT_DST, which is bound to prevent some optimization opportunities. Worse, it mislead the heuristic that decides whether immediates should be lowered to S_MOV_B32 or V_MOV_B32 in a way that resulted in unnecessary v_readfirstlanes. Reviewers: arsenm, tstellarAMD Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D22217 llvm-svn: 275160
This commit is contained in:
Nicolai Haehnle
parent
7899d48dff
commit
7968c34586
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@ -129,10 +129,7 @@ private:
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bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const;
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bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const;
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bool SelectSMRDBufferSgpr(SDValue Addr, SDValue &Offset) const;
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bool selectMOVRELOffsetImpl(SDValue Index, SDValue &Base,
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SDValue &Offset, bool IsInsert) const;
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bool selectMOVRELSOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;
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bool selectMOVRELDOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;
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bool SelectMOVRELOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;
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bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
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bool SelectVOP3NoMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
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bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
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@ -1193,10 +1190,9 @@ bool AMDGPUDAGToDAGISel::SelectSMRDBufferSgpr(SDValue Addr,
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!isa<ConstantSDNode>(Offset);
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}
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bool AMDGPUDAGToDAGISel::selectMOVRELOffsetImpl(SDValue Index,
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SDValue &Base,
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SDValue &Offset,
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bool IsInsert) const {
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bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index,
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SDValue &Base,
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SDValue &Offset) const {
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SDLoc DL(Index);
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if (CurDAG->isBaseWithConstantOffset(Index)) {
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@ -1210,34 +1206,14 @@ bool AMDGPUDAGToDAGISel::selectMOVRELOffsetImpl(SDValue Index,
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return true;
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}
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if (IsInsert) {
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if (ConstantSDNode *CBase = dyn_cast<ConstantSDNode>(Index)) {
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Base = CurDAG->getRegister(AMDGPU::NoRegister, MVT::i32);
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Offset = CurDAG->getTargetConstant(CBase->getZExtValue(), DL, MVT::i32);
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return true;
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}
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} else {
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if (isa<ConstantSDNode>(Index))
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return false;
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}
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if (isa<ConstantSDNode>(Index))
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return false;
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Base = Index;
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Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
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return true;
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}
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bool AMDGPUDAGToDAGISel::selectMOVRELSOffset(SDValue Index,
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SDValue &Base,
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SDValue &Offset) const {
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return selectMOVRELOffsetImpl(Index, Base, Offset, false);
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}
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bool AMDGPUDAGToDAGISel::selectMOVRELDOffset(SDValue Index,
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SDValue &Base,
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SDValue &Offset) const {
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return selectMOVRELOffsetImpl(Index, Base, Offset, true);
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}
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SDNode *AMDGPUDAGToDAGISel::getS_BFE(unsigned Opcode, const SDLoc &DL,
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SDValue Val, uint32_t Offset,
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uint32_t Width) {
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@ -624,8 +624,7 @@ def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
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def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
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def SMRDBufferSgpr : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
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def MOVRELSOffset : ComplexPattern<i32, 2, "selectMOVRELSOffset">;
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def MOVRELDOffset : ComplexPattern<i32, 2, "selectMOVRELDOffset">;
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def MOVRELOffset : ComplexPattern<i32, 2, "SelectMOVRELOffset">;
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def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
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def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">;
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@ -3308,13 +3308,13 @@ def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
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multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> {
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// Extract with offset
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def : Pat<
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(eltvt (extractelt vt:$src, (MOVRELSOffset i32:$idx, (i32 imm:$offset)))),
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(eltvt (extractelt vt:$src, (MOVRELOffset i32:$idx, (i32 imm:$offset)))),
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(!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $src, $idx, imm:$offset)
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>;
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// Insert with offset
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def : Pat<
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(insertelt vt:$src, eltvt:$val, (MOVRELDOffset i32:$idx, (i32 imm:$offset))),
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(insertelt vt:$src, eltvt:$val, (MOVRELOffset i32:$idx, (i32 imm:$offset))),
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(!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $src, $idx, imm:$offset, $val)
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>;
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}
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@ -73,6 +73,15 @@ define void @insertelement_v3f32_3(<3 x float> addrspace(1)* %out, <3 x float> %
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ret void
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}
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; GCN-LABEL: {{^}}insertelement_to_sgpr:
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; GCN-NOT: v_readfirstlane
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define amdgpu_ps <4 x float> @insertelement_to_sgpr() nounwind {
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%tmp = load <4 x i32>, <4 x i32> addrspace(2)* undef
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%tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0
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%tmp2 = call <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> %tmp1, i32 8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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ret <4 x float> %tmp2
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}
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; GCN-LABEL: {{^}}dynamic_insertelement_v2f32:
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; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000
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; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]]
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@ -432,3 +441,5 @@ define void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)* %out, <8 x d
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store <8 x double> %vecins, <8 x double> addrspace(1)* %out, align 16
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ret void
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}
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declare <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) nounwind readnone
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@ -467,12 +467,9 @@ main_body:
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; This crashed at some point due to a bug in FixSGPRCopies. Derived from the
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; report in https://bugs.freedesktop.org/show_bug.cgi?id=96877
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;
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;TODO: the readfirstlanes are unnecessary, see http://reviews.llvm.org/D22217
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;
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;CHECK: v_readfirstlane_b32 s[[LO:[0-9]+]], v{{[0-9]+}}
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;CHECK: v_readfirstlane_b32
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;CHECK: v_readfirstlane_b32
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;CHECK: v_readfirstlane_b32 s[[HI:[0-9]+]], v{{[0-9]+}}
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;CHECK: s_load_dwordx4 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0
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;CHECK: s_waitcnt lgkmcnt(0)
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;CHECK: s_mov_b32 s[[LO]], 0
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;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, s{{\[}}[[LO]]:[[HI]]] dmask:0x8
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define amdgpu_ps float @gather4_sgpr_bug() {
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main_body:
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