AMDGPU: Fold bitcasts of scalar constants to vectors
This cleans up some messes since the individual scalar components can be CSEed. llvm-svn: 266376
This commit is contained in:
Matt Arsenault
parent
34b60f1c40
commit
7900334dd5
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@ -399,6 +399,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
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setTargetDAGCombine(ISD::FADD);
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setTargetDAGCombine(ISD::FSUB);
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setTargetDAGCombine(ISD::BITCAST);
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setBooleanContents(ZeroOrNegativeOneBooleanContent);
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setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
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@ -2547,6 +2549,38 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
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switch(N->getOpcode()) {
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default:
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break;
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case ISD::BITCAST: {
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EVT DestVT = N->getValueType(0);
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if (DestVT.getSizeInBits() != 64 && !DestVT.isVector())
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break;
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// Fold bitcasts of constants.
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//
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// v2i32 (bitcast i64:k) -> build_vector lo_32(k), hi_32(k)
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// TODO: Generalize and move to DAGCombiner
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SDValue Src = N->getOperand(0);
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src)) {
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assert(Src.getValueType() == MVT::i64);
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SDLoc SL(N);
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uint64_t CVal = C->getZExtValue();
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return DAG.getNode(ISD::BUILD_VECTOR, SL, DestVT,
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DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
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DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
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}
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if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Src)) {
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const APInt &Val = C->getValueAPF().bitcastToAPInt();
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SDLoc SL(N);
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uint64_t CVal = Val.getZExtValue();
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SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
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DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
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DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
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return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);
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}
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break;
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}
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case ISD::SHL: {
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if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
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break;
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@ -1,4 +1,4 @@
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
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@ -25,7 +25,7 @@ declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone
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; SI-DAG: cndmask_b32
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; SI-DAG: v_cmp_lt_f64
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; SI-DAG: v_cmp_lg_f64
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; SI: s_and_b64
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; SI-DAG: s_and_b64
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; SI: v_cndmask_b32
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; SI: v_cndmask_b32
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; SI: v_add_f64
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@ -1,8 +1,8 @@
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;RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC %s
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;RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC %s
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;RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC %s
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;RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s
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;FUNC-LABEL: {{^}}test_sdiv:
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;FUNC-LABEL: {{^}}s_test_sdiv:
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;EG: RECIP_UINT
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;EG: LSHL {{.*}}, 1,
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;EG: BFE_UINT
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@ -36,47 +36,47 @@
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;EG: BFE_UINT
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;EG: BFE_UINT
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN: v_bfe_u32
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;GCN-NOT: v_mad_f32
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;SI-NOT: v_lshr_b64
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;VI-NOT: v_lshrrev_b64
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;GCN: s_endpgm
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define void @test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN: s_bfe_u32
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; GCN-NOT: v_mad_f32
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; SI-NOT: v_lshr_b64
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; VI-NOT: v_lshrrev_b64
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; GCN: s_endpgm
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define void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
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%result = sdiv i64 %x, %y
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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;FUNC-LABEL: {{^}}test_srem:
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;FUNC-LABEL: {{^}}s_test_srem:
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;EG: RECIP_UINT
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;EG: BFE_UINT
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;EG: BFE_UINT
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@ -144,7 +144,7 @@ define void @test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
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;SI-NOT: v_lshr_b64
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;VI-NOT: v_lshrrev_b64
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;GCN: s_endpgm
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define void @test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
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define void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
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%result = urem i64 %x, %y
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store i64 %result, i64 addrspace(1)* %out
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ret void
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@ -1,4 +1,4 @@
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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@ -10,14 +10,14 @@ define void @sint_to_fp_i32_to_f64(double addrspace(1)* %out, i32 %in) {
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ret void
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}
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; FIXME: select on 0, 0
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; SI-LABEL: {{^}}sint_to_fp_i1_f64:
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; SI: v_cmp_eq_i32_e64 vcc,
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; We can't fold the SGPRs into v_cndmask_b32_e64, because it already
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; uses an SGPR (implicit vcc).
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; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
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; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 0, vcc
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; SI: buffer_store_dwordx2
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; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}}
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; SI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
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; SI: buffer_store_dwordx2 v{{\[}}[[ZERO]]:[[SEL]]{{\]}}
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; SI: s_endpgm
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define void @sint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) {
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%cmp = icmp eq i32 %in, 0
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@ -70,14 +70,13 @@ define void @s_uint_to_fp_v4i32_to_v4f64(<4 x double> addrspace(1)* %out, <4 x i
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ret void
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}
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; FIXME: select on 0, 0
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; SI-LABEL: {{^}}uint_to_fp_i1_to_f64:
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; SI: v_cmp_eq_i32_e64 vcc
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; We can't fold the SGPRs into v_cndmask_b32_e32, because it already
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; uses an SGPR (implicit vcc).
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; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
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; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 0, vcc
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; SI: buffer_store_dwordx2
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; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}}
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; SI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
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; SI: buffer_store_dwordx2 v{{\[}}[[ZERO]]:[[SEL]]{{\]}}
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; SI: s_endpgm
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define void @uint_to_fp_i1_to_f64(double addrspace(1)* %out, i32 %in) {
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%cmp = icmp eq i32 %in, 0
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