Allow pointer constants as well as integer and booleans.
Skip over list nodes in ForwardOperand. llvm-svn: 617
This commit is contained in:
Vikram S. Adve
parent
49d908a419
commit
78d50d0f7a
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@ -1,3 +1,4 @@
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// $Id$
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//***************************************************************************
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// File:
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// SparcInstrSelection.cpp
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@ -95,7 +96,7 @@ static MachineInstr* MakeLoadConstInstr(Instruction* vmInstr,
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MachineInstr*& getMinstr2);
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static void ForwardOperand (InstructionNode* treeNode,
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InstructionNode* parent,
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InstrTreeNode* parent,
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int operandNum);
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@ -104,14 +105,16 @@ static void ForwardOperand (InstructionNode* treeNode,
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// Convenience function to get the value of an integer constant, for an
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// appropriate integer or non-integer type that can be held in an integer.
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// The type of the argument must be the following:
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// GetConstantValueAsSignedInt: any of the above, but the value
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// must fit into a int64_t.
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// Signed or unsigned integer
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// Boolean
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// Pointer
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//
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// isValidConstant is set to true if a valid constant was found.
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//
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static int64_t GetConstantValueAsSignedInt(const Value *V,
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bool &isValidConstant) {
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static int64_t
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GetConstantValueAsSignedInt(const Value *V,
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bool &isValidConstant)
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{
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if (!V->isConstant()) { isValidConstant = false; return 0; }
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isValidConstant = true;
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@ -161,10 +164,20 @@ ThisIsAChainRule(int eruleno)
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case 130:
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case 131:
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case 132:
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case 133:
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case 153:
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case 155: return true; break;
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case 155:
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case 221:
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case 222:
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case 232:
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case 241:
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case 242:
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case 243:
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case 244:
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return true; break;
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default: return false; break;
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default:
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return false; break;
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}
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}
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@ -305,7 +318,7 @@ ChooseMovFpccInstruction(const InstructionNode* instrNode)
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// Set mustClearReg=false if v3 need not be cleared before conditional move.
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// Set valueToMove=0 if we want to conditionally move 0 instead of 1
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// (i.e., we want to test inverse of a condition)
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//
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// (The latter two cases do not seem to arise because SetNE needs nothing.)
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//
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static MachineOpCode
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ChooseMovpccAfterSub(const InstructionNode* instrNode,
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@ -318,18 +331,13 @@ ChooseMovpccAfterSub(const InstructionNode* instrNode,
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switch(instrNode->getInstruction()->getOpcode())
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{
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case Instruction::SetEQ: opCode = MOVNE; mustClearReg = false;
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valueToMove = 0; break;
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case Instruction::SetEQ: opCode = MOVE; break;
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case Instruction::SetLE: opCode = MOVLE; break;
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case Instruction::SetGE: opCode = MOVGE; break;
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case Instruction::SetLT: opCode = MOVL; break;
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case Instruction::SetGT: opCode = MOVG; break;
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case Instruction::SetNE: assert(0 && "No move required!");
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default:
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assert(0 && "Unrecognized VM instruction!");
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break;
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case Instruction::SetNE: assert(0 && "No move required!"); break;
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default: assert(0 && "Unrecognized VM instr!"); break;
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}
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return opCode;
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@ -627,7 +635,7 @@ CreateMulConstInstruction(const InstructionNode* instrNode,
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//
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const Type* resultType = instrNode->getInstruction()->getType();
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if (resultType->isIntegral())
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if (resultType->isIntegral() || resultType->isPointerType())
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{
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unsigned pow;
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bool isValidConst;
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@ -1247,12 +1255,23 @@ MakeLoadConstInstr(Instruction* vmInstr,
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//
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static void
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ForwardOperand(InstructionNode* treeNode,
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InstructionNode* parent,
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InstrTreeNode* parent,
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int operandNum)
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{
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assert(treeNode && parent && "Invalid invocation of ForwardOperand");
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Instruction* unusedOp = treeNode->getInstruction();
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Value* fwdOp = unusedOp->getOperand(operandNum);
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Instruction* userInstr = parent->getInstruction();
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// The parent itself may be a list node, so find the real parent instruction
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while (parent->getNodeType() != InstrTreeNode::NTInstructionNode)
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{
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parent = parent->parent();
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assert(parent && "ERROR: Non-instruction node has no parent in tree.");
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}
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InstructionNode* parentInstrNode = (InstructionNode*) parent;
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Instruction* userInstr = parentInstrNode->getInstruction();
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MachineCodeForVMInstr& mvec = userInstr->getMachineInstrVec();
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for (unsigned i=0, N=mvec.size(); i < N; i++)
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{
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@ -1316,7 +1335,6 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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const Type* opType;
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int nextRule;
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int forwardOperandNum = -1;
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BranchPattern brPattern;
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int64_t s0 = 0; // variables holding zero to avoid
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uint64_t u0 = 0; // overloading ambiguities below
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@ -1359,8 +1377,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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mvec[numInstr++] = new MachineInstr(NOP);
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break;
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case 6: // stmt: BrCond(boolconst)
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// boolconst => boolean was computed with `%b = setCC type reg1 constant'
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case 206: // stmt: BrCond(setCCconst)
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// setCCconst => boolean was computed with `%b = setCC type reg1 constant'
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// If the constant is ZERO, we can use the branch-on-integer-register
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// instructions and avoid the SUBcc instruction entirely.
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// Otherwise this is just the same as case 5, so just fall through.
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@ -1370,11 +1388,12 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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ConstPoolVal* constVal = (ConstPoolVal*) constNode->getValue();
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bool isValidConst;
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if (constVal->getType()->isIntegral()
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if ((constVal->getType()->isIntegral()
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|| constVal->getType()->isPointerType())
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&& GetConstantValueAsSignedInt(constVal, isValidConst) == 0
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&& isValidConst)
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{
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// That constant ia a zero after all...
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// That constant is a zero after all...
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// Use the left child of the setCC instruction as the first argument!
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mvec[0] = new MachineInstr(ChooseBprInstruction(subtreeRoot));
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mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
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@ -1399,8 +1418,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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// ELSE FALL THROUGH
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}
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case 7: // stmt: BrCond(bool)
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// bool => boolean was computed with `%b = setcc type reg1 reg2'
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case 6: // stmt: BrCond(bool)
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// bool => boolean was computed with some boolean operator (setCC,Not,...)
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// Need to check whether the type was a FP, signed int or unsigned int,
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// and check the branching condition in order to choose the branch to use.
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//
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@ -1427,8 +1446,10 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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break;
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}
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case 8: // stmt: BrCond(boolreg)
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// bool => boolean is stored in an existing register.
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case 8: // stmt: BrCond(boolreg)
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case 208: // stmt: BrCond(boolconst)
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// boolreg => boolean is stored in an existing register.
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// boolconst => boolean is a constant; can be loaded into a register.
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// Just use the branch-on-integer-register instruction!
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//
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mvec[0] = new MachineInstr(BRNZ);
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@ -1439,7 +1460,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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// delay slot
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mvec[numInstr++] = new MachineInstr(NOP); // delay slot
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// false branch
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mvec[numInstr++] = new MachineInstr(BA);
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mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
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@ -1469,6 +1490,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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subtreeRoot->getValue());
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break;
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case 322: // reg: ToBoolTy(bool):
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case 22: // reg: ToBoolTy(reg):
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opType = subtreeRoot->leftChild()->getValue()->getType();
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assert(opType->isIntegral() || opType == Type::BoolTy);
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@ -1693,8 +1715,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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if (subtreeRoot->leftChild()->getValue()->getType()->isIntegral() ||
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subtreeRoot->leftChild()->getValue()->getType()->isPointerType())
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{
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// integer condition: destination should be %g0 or integer register
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// if result must be saved but condition is not SetEQ then we need
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// Integer condition: destination should be %g0 or integer register.
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// If result must be saved but condition is not SetEQ then we need
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// a separate instruction to compute the bool result, so discard
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// result of SUBcc instruction anyway.
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//
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@ -1914,14 +1936,18 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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case 62: // reg: Shl(reg, reg)
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opType = subtreeRoot->leftChild()->getValue()->getType();
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assert(opType->isIntegral() || opType == Type::BoolTy);
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assert(opType->isIntegral()
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|| opType == Type::BoolTy
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|| opType->isPointerType() && "Shl unsupported for other types");
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mvec[0] = new MachineInstr((opType == Type::LongTy)? SLLX : SLL);
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Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
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break;
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case 63: // reg: Shr(reg, reg)
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opType = subtreeRoot->leftChild()->getValue()->getType();
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assert(opType->isIntegral() || opType == Type::BoolTy);
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assert(opType->isIntegral()
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|| opType == Type::BoolTy
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|| opType->isPointerType() && "Shr unsupported for other types");
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mvec[0] = new MachineInstr((opType->isSigned()
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? ((opType == Type::LongTy)? SRAX : SRA)
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: ((opType == Type::LongTy)? SRLX : SRL)));
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@ -1959,8 +1985,16 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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case 130:
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case 131:
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case 132:
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case 133:
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case 153:
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case 155:
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case 221:
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case 222:
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case 232:
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case 241:
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case 242:
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case 243:
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case 244:
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//
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// These are all chain rules, which have a single nonterminal on the RHS.
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// Get the rule that matches the RHS non-terminal and use that instead.
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@ -1985,8 +2019,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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// If not, insert a copy instruction which should get coalesced away
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// by register allocation.
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if (subtreeRoot->parent() != NULL)
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ForwardOperand(subtreeRoot, (InstructionNode*) subtreeRoot->parent(),
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forwardOperandNum);
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ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
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else
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{
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int n = numInstr++;
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