Fix for PR1306.
- A register def / use now implicitly affects sub-register liveness but does not affect liveness information of super-registers. - Def of a larger register (if followed by a use later) is treated as read/mod/write of a smaller register. llvm-svn: 36434
This commit is contained in:
parent
93e3a2e6f7
commit
7818c03c6b
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@ -255,7 +255,7 @@ namespace llvm {
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/// handleLiveInRegister - Create interval for a livein register.
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/// handleLiveInRegister - Create interval for a livein register.
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void handleLiveInRegister(MachineBasicBlock* mbb,
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void handleLiveInRegister(MachineBasicBlock* mbb,
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unsigned MIIdx,
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unsigned MIIdx,
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LiveInterval &interval);
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LiveInterval &interval, bool isAlias = false);
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/// Return true if the two specified registers belong to different
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/// Return true if the two specified registers belong to different
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/// register classes. The registers may be either phys or virt regs.
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/// register classes. The registers may be either phys or virt regs.
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@ -124,8 +124,25 @@ private: // Intermediate data structures
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const MRegisterInfo *RegInfo;
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const MRegisterInfo *RegInfo;
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MachineInstr **PhysRegInfo;
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// PhysRegInfo - Keep track of which instruction was the last def/use of a
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bool *PhysRegUsed;
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// physical register. This is a purely local property, because all physical
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// register references as presumed dead across basic blocks.
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std::vector<MachineInstr*> PhysRegInfo;
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// PhysRegUsed - Keep track whether the physical register has been used after
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// its last definition. This is local property.
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BitVector PhysRegUsed;
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// PhysRegPartDef - Keep track of a list of instructions which "partially"
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// defined the physical register (e.g. on X86 AX partially defines EAX).
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// These are turned into use/mod/write if there is a use of the register
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// later in the same block. This is local property.
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std::vector<std::vector<MachineInstr*> > PhysRegPartDef;
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// PhysRegPartUse - Keep track of which instruction was the last partial use
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// of a physical register (e.g. on X86 a def of EAX followed by a use of AX).
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// This is a purely local property.
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std::vector<MachineInstr*> PhysRegPartUse;
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typedef std::map<const MachineBasicBlock*,
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typedef std::map<const MachineBasicBlock*,
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std::vector<unsigned> > PHIVarInfoMap;
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std::vector<unsigned> > PHIVarInfoMap;
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@ -675,8 +675,12 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
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exit:
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exit:
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assert(start < end && "did not find end of interval?");
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assert(start < end && "did not find end of interval?");
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LiveRange LR(start, end, interval.getNextValue(SrcReg != 0 ? start : ~0U,
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// Already exists? Extend old live interval.
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SrcReg));
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LiveInterval::iterator OldLR = interval.FindLiveRangeContaining(start);
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unsigned Id = (OldLR != interval.end())
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? OldLR->ValId
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: interval.getNextValue(SrcReg != 0 ? start : ~0U, SrcReg);
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LiveRange LR(start, end, Id);
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interval.addRange(LR);
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interval.addRange(LR);
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DOUT << " +" << LR << '\n';
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DOUT << " +" << LR << '\n';
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}
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}
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@ -692,14 +696,17 @@ void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
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if (!tii_->isMoveInstr(*MI, SrcReg, DstReg))
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if (!tii_->isMoveInstr(*MI, SrcReg, DstReg))
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SrcReg = 0;
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SrcReg = 0;
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handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg);
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handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg);
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for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
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// Def of a register also defines its sub-registers.
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handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
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for (const unsigned* AS = mri_->getSubRegisters(reg); *AS; ++AS)
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// Avoid processing some defs more than once.
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if (!MI->findRegisterDefOperand(*AS))
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handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
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}
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}
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}
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}
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void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
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void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
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unsigned MIIdx,
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unsigned MIIdx,
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LiveInterval &interval) {
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LiveInterval &interval, bool isAlias) {
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DOUT << "\t\tlivein register: "; DEBUG(printRegName(interval.reg));
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DOUT << "\t\tlivein register: "; DEBUG(printRegName(interval.reg));
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// Look for kills, if it reaches a def before it's killed, then it shouldn't
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// Look for kills, if it reaches a def before it's killed, then it shouldn't
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@ -728,6 +735,12 @@ void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
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}
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}
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exit:
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exit:
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// Alias of a live-in register might not be used at all.
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if (isAlias && end == 0) {
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DOUT << " dead";
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end = getDefIndex(start) + 1;
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}
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assert(start < end && "did not find end of interval?");
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assert(start < end && "did not find end of interval?");
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LiveRange LR(start, end, interval.getNextValue(~0U, 0));
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LiveRange LR(start, end, interval.getNextValue(~0U, 0));
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@ -757,8 +770,10 @@ void LiveIntervals::computeIntervals() {
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for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(),
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for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(),
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LE = MBB->livein_end(); LI != LE; ++LI) {
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LE = MBB->livein_end(); LI != LE; ++LI) {
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handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
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handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
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for (const unsigned* AS = mri_->getAliasSet(*LI); *AS; ++AS)
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// Multiple live-ins can alias the same register.
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handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS));
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for (const unsigned* AS = mri_->getSubRegisters(*LI); *AS; ++AS)
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if (!hasInterval(*AS))
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handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS), true);
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}
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}
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}
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}
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@ -856,7 +871,8 @@ bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
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// If the IntB live range is assigned to a physical register, and if that
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// If the IntB live range is assigned to a physical register, and if that
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// physreg has aliases,
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// physreg has aliases,
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if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
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if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
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for (const unsigned *AS = mri_->getAliasSet(IntB.reg); *AS; ++AS) {
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// Update the liveintervals of sub-registers.
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for (const unsigned *AS = mri_->getSubRegisters(IntB.reg); *AS; ++AS) {
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LiveInterval &AliasLI = getInterval(*AS);
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LiveInterval &AliasLI = getInterval(*AS);
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AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
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AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
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AliasLI.getNextValue(~0U, 0)));
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AliasLI.getNextValue(~0U, 0)));
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@ -1055,8 +1071,9 @@ bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
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// we have to update any aliased register's live ranges to indicate that they
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// we have to update any aliased register's live ranges to indicate that they
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// have clobbered values for this range.
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// have clobbered values for this range.
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if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
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if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
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for (const unsigned *AS = mri_->getAliasSet(repDstReg); *AS; ++AS)
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// Update the liveintervals of sub-registers.
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getInterval(*AS).MergeInClobberRanges(SrcInt);
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for (const unsigned *AS = mri_->getSubRegisters(repDstReg); *AS; ++AS)
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getInterval(*AS).MergeInClobberRanges(SrcInt);
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} else {
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} else {
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// Merge use info if the destination is a virtual register.
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// Merge use info if the destination is a virtual register.
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LiveVariables::VarInfo& dVI = lv_->getVarInfo(repDstReg);
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LiveVariables::VarInfo& dVI = lv_->getVarInfo(repDstReg);
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@ -1279,6 +1296,27 @@ bool LiveIntervals::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS) {
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SmallVector<int, 16> LHSValNoAssignments;
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SmallVector<int, 16> LHSValNoAssignments;
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SmallVector<int, 16> RHSValNoAssignments;
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SmallVector<int, 16> RHSValNoAssignments;
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SmallVector<std::pair<unsigned,unsigned>, 16> ValueNumberInfo;
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SmallVector<std::pair<unsigned,unsigned>, 16> ValueNumberInfo;
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// If a live interval is a physical register, conservatively check if any
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// of its sub-registers is overlapping the live interval of the virtual
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// register. If so, do not coalesce.
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if (MRegisterInfo::isPhysicalRegister(LHS.reg) &&
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*mri_->getSubRegisters(LHS.reg)) {
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for (const unsigned* SR = mri_->getSubRegisters(LHS.reg); *SR; ++SR)
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if (hasInterval(*SR) && RHS.overlaps(getInterval(*SR))) {
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DOUT << "Interfere with sub-register ";
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DEBUG(getInterval(*SR).print(DOUT, mri_));
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return false;
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}
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} else if (MRegisterInfo::isPhysicalRegister(RHS.reg) &&
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*mri_->getSubRegisters(RHS.reg)) {
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for (const unsigned* SR = mri_->getSubRegisters(RHS.reg); *SR; ++SR)
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if (hasInterval(*SR) && LHS.overlaps(getInterval(*SR))) {
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DOUT << "Interfere with sub-register ";
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DEBUG(getInterval(*SR).print(DOUT, mri_));
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return false;
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}
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}
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// Compute ultimate value numbers for the LHS and RHS values.
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// Compute ultimate value numbers for the LHS and RHS values.
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if (RHS.containsOneValue()) {
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if (RHS.containsOneValue()) {
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@ -77,7 +77,10 @@ bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isKill()) {
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if (MO.isReg() && MO.isKill()) {
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if (RegInfo->regsOverlap(Reg, MO.getReg()))
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if ((MO.getReg() == Reg) ||
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(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
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MRegisterInfo::isPhysicalRegister(Reg) &&
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RegInfo->isSubRegister(MO.getReg(), Reg)))
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return true;
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return true;
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}
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}
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}
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}
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@ -87,9 +90,13 @@ bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
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bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
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bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isDead())
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if (MO.isReg() && MO.isDead()) {
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if (RegInfo->regsOverlap(Reg, MO.getReg()))
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if ((MO.getReg() == Reg) ||
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(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
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MRegisterInfo::isPhysicalRegister(Reg) &&
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RegInfo->isSubRegister(MO.getReg(), Reg)))
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return true;
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return true;
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}
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}
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}
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return false;
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return false;
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}
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}
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@ -97,10 +104,8 @@ bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
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bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
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bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isDef()) {
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if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
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if (RegInfo->regsOverlap(Reg, MO.getReg()))
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return true;
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return true;
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}
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}
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}
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return false;
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return false;
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}
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}
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@ -166,57 +171,145 @@ void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
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}
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}
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void LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI) {
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void LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI) {
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bool Found = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isUse() && MO.getReg() == IncomingReg) {
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if (MO.isReg() && MO.isUse()) {
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MO.setIsKill();
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unsigned Reg = MO.getReg();
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break;
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if (!Reg)
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continue;
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if (Reg == IncomingReg) {
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MO.setIsKill();
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Found = true;
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break;
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} else if (MRegisterInfo::isPhysicalRegister(Reg) &&
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MRegisterInfo::isPhysicalRegister(IncomingReg) &&
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RegInfo->isSuperRegister(IncomingReg, Reg) &&
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MO.isKill())
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// A super-register kill already exists.
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return;
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}
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}
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}
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}
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// If not found, this means an alias of one of the operand is killed. Add a
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// new implicit operand.
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if (!Found)
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MI->addRegOperand(IncomingReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
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}
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}
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void LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI) {
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void LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI) {
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bool Found = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isDef() && MO.getReg() == IncomingReg) {
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if (MO.isReg() && MO.isDef()) {
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MO.setIsDead();
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unsigned Reg = MO.getReg();
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break;
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if (!Reg)
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continue;
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if (Reg == IncomingReg) {
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MO.setIsDead();
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Found = true;
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break;
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} else if (MRegisterInfo::isPhysicalRegister(Reg) &&
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MRegisterInfo::isPhysicalRegister(IncomingReg) &&
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RegInfo->isSuperRegister(IncomingReg, Reg) &&
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MO.isDead())
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// There exists a super-register that's marked dead.
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return;
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}
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}
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}
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}
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// If not found, this means an alias of one of the operand is dead. Add a
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// new implicit operand.
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if (!Found)
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MI->addRegOperand(IncomingReg, true/*IsDef*/,true/*IsImp*/,false/*IsKill*/,
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true/*IsDead*/);
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}
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}
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void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
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void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
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// There is a now a proper use, forget about the last partial use.
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PhysRegPartUse[Reg] = NULL;
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// Turn previous partial def's into read/mod/write.
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for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) {
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MachineInstr *Def = PhysRegPartDef[Reg][i];
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// First one is just a def. This means the use is reading some undef bits.
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if (i != 0)
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Def->addRegOperand(Reg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
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Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
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}
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PhysRegPartDef[Reg].clear();
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// There was an earlier def of a super-register. Add implicit def to that MI.
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// A: EAX = ...
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// B: = AX
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// Add implicit def to A.
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if (PhysRegInfo[Reg] && !PhysRegUsed[Reg]) {
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MachineInstr *Def = PhysRegInfo[Reg];
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if (!Def->findRegisterDefOperand(Reg))
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Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
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}
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PhysRegInfo[Reg] = MI;
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PhysRegInfo[Reg] = MI;
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PhysRegUsed[Reg] = true;
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PhysRegUsed[Reg] = true;
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for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
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for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
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unsigned Alias = *AliasSet; ++AliasSet) {
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unsigned SubReg = *SubRegs; ++SubRegs) {
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PhysRegInfo[Alias] = MI;
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PhysRegInfo[SubReg] = MI;
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PhysRegUsed[Alias] = true;
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PhysRegUsed[SubReg] = true;
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}
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}
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// Remember the partial uses.
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for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
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unsigned SuperReg = *SuperRegs; ++SuperRegs)
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PhysRegPartUse[SuperReg] = MI;
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}
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}
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void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
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void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
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// Does this kill a previous version of this register?
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// Does this kill a previous version of this register?
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if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
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if (MachineInstr *LastRef = PhysRegInfo[Reg]) {
|
||||||
if (PhysRegUsed[Reg])
|
if (PhysRegUsed[Reg])
|
||||||
addRegisterKilled(Reg, LastUse);
|
addRegisterKilled(Reg, LastRef);
|
||||||
|
else if (PhysRegPartUse[Reg])
|
||||||
|
// Add implicit use / kill to last use of a sub-register.
|
||||||
|
addRegisterKilled(Reg, PhysRegPartUse[Reg]);
|
||||||
else
|
else
|
||||||
addRegisterDead(Reg, LastUse);
|
addRegisterDead(Reg, LastRef);
|
||||||
}
|
}
|
||||||
PhysRegInfo[Reg] = MI;
|
PhysRegInfo[Reg] = MI;
|
||||||
PhysRegUsed[Reg] = false;
|
PhysRegUsed[Reg] = false;
|
||||||
|
PhysRegPartUse[Reg] = NULL;
|
||||||
|
|
||||||
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
|
for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
|
||||||
unsigned Alias = *AliasSet; ++AliasSet) {
|
unsigned SubReg = *SubRegs; ++SubRegs) {
|
||||||
if (MachineInstr *LastUse = PhysRegInfo[Alias]) {
|
if (MachineInstr *LastRef = PhysRegInfo[SubReg]) {
|
||||||
if (PhysRegUsed[Alias])
|
if (PhysRegUsed[SubReg])
|
||||||
addRegisterKilled(Alias, LastUse);
|
addRegisterKilled(SubReg, LastRef);
|
||||||
|
else if (PhysRegPartUse[SubReg])
|
||||||
|
// Add implicit use / kill to last use of a sub-register.
|
||||||
|
addRegisterKilled(SubReg, PhysRegPartUse[SubReg]);
|
||||||
else
|
else
|
||||||
addRegisterDead(Alias, LastUse);
|
addRegisterDead(SubReg, LastRef);
|
||||||
}
|
}
|
||||||
PhysRegInfo[Alias] = MI;
|
PhysRegInfo[SubReg] = MI;
|
||||||
PhysRegUsed[Alias] = false;
|
PhysRegUsed[SubReg] = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (MI)
|
||||||
|
for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
|
||||||
|
unsigned SuperReg = *SuperRegs; ++SuperRegs) {
|
||||||
|
if (PhysRegInfo[SuperReg]) {
|
||||||
|
// The larger register is previously defined. Now a smaller part is
|
||||||
|
// being re-defined. Treat it as read/mod/write.
|
||||||
|
// EAX =
|
||||||
|
// AX = EAX<imp-use,kill>, EAX<imp-def>
|
||||||
|
MI->addRegOperand(SuperReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
|
||||||
|
MI->addRegOperand(SuperReg, true/*IsDef*/,true/*IsImp*/);
|
||||||
|
PhysRegInfo[SuperReg] = MI;
|
||||||
|
PhysRegUsed[SuperReg] = false;
|
||||||
|
} else {
|
||||||
|
// Remember this partial def.
|
||||||
|
PhysRegPartDef[SuperReg].push_back(MI);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -228,14 +321,10 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
|
||||||
|
|
||||||
ReservedRegisters = RegInfo->getReservedRegs(mf);
|
ReservedRegisters = RegInfo->getReservedRegs(mf);
|
||||||
|
|
||||||
// PhysRegInfo - Keep track of which instruction was the last use of a
|
PhysRegInfo.resize(RegInfo->getNumRegs(), (MachineInstr*)NULL);
|
||||||
// physical register. This is a purely local property, because all physical
|
PhysRegUsed.resize(RegInfo->getNumRegs());
|
||||||
// register references as presumed dead across basic blocks.
|
PhysRegPartDef.resize(RegInfo->getNumRegs());
|
||||||
//
|
PhysRegPartUse.resize(RegInfo->getNumRegs(), (MachineInstr*)NULL);
|
||||||
PhysRegInfo = (MachineInstr**)alloca(sizeof(MachineInstr*) *
|
|
||||||
RegInfo->getNumRegs());
|
|
||||||
PhysRegUsed = (bool*)alloca(sizeof(bool)*RegInfo->getNumRegs());
|
|
||||||
std::fill(PhysRegInfo, PhysRegInfo+RegInfo->getNumRegs(), (MachineInstr*)0);
|
|
||||||
|
|
||||||
/// Get some space for a respectable number of registers...
|
/// Get some space for a respectable number of registers...
|
||||||
VirtRegInfo.resize(64);
|
VirtRegInfo.resize(64);
|
||||||
|
@ -342,6 +431,12 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
|
||||||
for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
|
for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
|
||||||
if (PhysRegInfo[i])
|
if (PhysRegInfo[i])
|
||||||
HandlePhysRegDef(i, 0);
|
HandlePhysRegDef(i, 0);
|
||||||
|
|
||||||
|
// Clear some states between BB's. These are purely local information.
|
||||||
|
for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i) {
|
||||||
|
PhysRegPartDef[i].clear();
|
||||||
|
PhysRegPartUse[i] = NULL;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
// Convert and transfer the dead / killed information we have gathered into
|
// Convert and transfer the dead / killed information we have gathered into
|
||||||
|
|
Loading…
Reference in New Issue